linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * SuperH Timer Support - TMU

 *

 *  Copyright (C) 2009 Magnus Damm

 */

​

#include <linux/clk.h>

#include <linux/clockchips.h>

#include <linux/clocksource.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/pm_domain.h>

#include <linux/pm_runtime.h>

#include <linux/sh_timer.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

enum sh_tmu_model {

    SH_TMU,

    SH_TMU_SH3,

};

​

struct sh_tmu_device;

​

struct sh_tmu_channel {

    struct sh_tmu_device *tmu;

    unsigned int index;

​

    void __iomem *base;

    int irq;

​

    unsigned long periodic;

    struct clock_event_device ced;

    struct clocksource cs;

    bool cs_enabled;

    unsigned int enable_count;

};

​

struct sh_tmu_device {

    struct platform_device *pdev;

​

    void __iomem *mapbase;

    struct clk *clk;

    unsigned long rate;

​

    enum sh_tmu_model model;

​

    raw_spinlock_t lock; /* Protect the shared start/stop register */

​

    struct sh_tmu_channel *channels;

    unsigned int num_channels;

​

    bool has_clockevent;

    bool has_clocksource;

};

​

#define TSTR -1 /* shared register */

#define TCOR  0 /* channel register */

#define TCNT 1 /* channel register */

#define TCR 2 /* channel register */

​

#define TCR_UNF         (1 << 8)

#define TCR_UNIE        (1 << 5)

#define TCR_TPSC_CLK4       (0 << 0)

#define TCR_TPSC_CLK16      (1 << 0)

#define TCR_TPSC_CLK64      (2 << 0)

#define TCR_TPSC_CLK256     (3 << 0)

#define TCR_TPSC_CLK1024    (4 << 0)

#define TCR_TPSC_MASK       (7 << 0)

​

static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)

{

    unsigned long offs;

​

    if (reg_nr == TSTR) {

        switch (ch->tmu->model) {

        case SH_TMU_SH3:

            return ioread8(ch->tmu->mapbase + 2);

        case SH_TMU:

            return ioread8(ch->tmu->mapbase + 4);

        }

    }

​