linux-imx

// SPDX-License-Identifier: GPL-2.0

#include <linux/init.h>

#include <linux/clocksource.h>

#include <linux/clockchips.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

​

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/ioport.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include <linux/syscore_ops.h>

#include <linux/atmel_tc.h>

​

​

/*

 * We're configured to use a specific TC block, one that's not hooked

 * up to external hardware, to provide a time solution:

 *

 *   - Two channels combine to create a free-running 32 bit counter

 *     with a base rate of 5+ MHz, packaged as a clocksource (with

 *     resolution better than 200 nsec).

 *   - Some chips support 32 bit counter. A single channel is used for

 *     this 32 bit free-running counter. the second channel is not used.

 *

 *   - The third channel may be used to provide a 16-bit clockevent

 *     source, used in either periodic or oneshot mode.  This runs

 *     at 32 KiHZ, and can handle delays of up to two seconds.

 *

 * A boot clocksource and clockevent source are also currently needed,

 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so

 * this code can be used when init_timers() is called, well before most

 * devices are set up.  (Some low end AT91 parts, which can run uClinux,

 * have only the timers in one TC block... they currently don't support

 * the tclib code, because of that initialization issue.)

 *

 * REVISIT behavior during system suspend states... we should disable

 * all clocks and save the power.  Easily done for clockevent devices,

 * but clocksources won't necessarily get the needed notifications.

 * For deeper system sleep states, this will be mandatory...

 */

​

static void __iomem *tcaddr;

static struct

{

    u32 cmr;

    u32 imr;

    u32 rc;

    bool clken;

} tcb_cache[3];

static u32 bmr_cache;

​

static u64 tc_get_cycles(struct clocksource *cs)

{

    unsigned long   flags;

    u32     lower, upper;

​

    raw_local_irq_save(flags);

    do {

        upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));

        lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));

    } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));

​

    raw_local_irq_restore(flags);

    return (upper << 16) | lower;

}

​

static u64 tc_get_cycles32(struct clocksource *cs)

{

    return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));

}

​

static void tc_clksrc_suspend(struct clocksource *cs)

{

    int i;

​

    for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {

        tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));

        tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));

        tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));

        tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &

                    ATMEL_TC_CLKSTA);

    }

​

    bmr_cache = readl(tcaddr + ATMEL_TC_BMR);

}

​

static void tc_clksrc_resume(struct clocksource *cs)

{

    int i;

​