linux-imx

/*

 * Marvell Armada 370/XP SoC timer handling.

 *

 * Copyright (C) 2012 Marvell

 *

 * Lior Amsalem <alior@marvell.com>

 * Gregory CLEMENT <gregory.clement@free-electrons.com>

 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 *

 * Timer 0 is used as free-running clocksource, while timer 1 is

 * used as clock_event_device.

 *

 * ---

 * Clocksource driver for Armada 370 and Armada XP SoC.

 * This driver implements one compatible string for each SoC, given

 * each has its own characteristics:

 *

 *   * Armada 370 has no 25 MHz fixed timer.

 *

 *   * Armada XP cannot work properly without such 25 MHz fixed timer as

 *     doing otherwise leads to using a clocksource whose frequency varies

 *     when doing cpufreq frequency changes.

 *

 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt

 */

​

#include <linux/init.h>

#include <linux/platform_device.h>

#include <linux/kernel.h>

#include <linux/clk.h>

#include <linux/cpu.h>

#include <linux/timer.h>

#include <linux/clockchips.h>

#include <linux/interrupt.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/of_address.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <linux/sched_clock.h>

#include <linux/percpu.h>

#include <linux/syscore_ops.h>

​

#include <asm/delay.h>

​

/*

 * Timer block registers.

 */

#define TIMER_CTRL_OFF      0x0000

#define  TIMER0_EN       BIT(0)

#define  TIMER0_RELOAD_EN    BIT(1)

#define  TIMER0_25MHZ            BIT(11)

#define  TIMER0_DIV(div)         ((div) << 19)

#define  TIMER1_EN       BIT(2)

#define  TIMER1_RELOAD_EN    BIT(3)

#define  TIMER1_25MHZ            BIT(12)

#define  TIMER1_DIV(div)         ((div) << 22)

#define TIMER_EVENTS_STATUS 0x0004

#define  TIMER0_CLR_MASK         (~0x1)

#define  TIMER1_CLR_MASK         (~0x100)

#define TIMER0_RELOAD_OFF   0x0010

#define TIMER0_VAL_OFF      0x0014

#define TIMER1_RELOAD_OFF   0x0018

#define TIMER1_VAL_OFF      0x001c

​

#define LCL_TIMER_EVENTS_STATUS 0x0028

/* Global timers are connected to the coherency fabric clock, and the

   below divider reduces their incrementing frequency. */

#define TIMER_DIVIDER_SHIFT     5

#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)

​

/*

 * SoC-specific data.

 */

static void __iomem *timer_base, *local_base;

static unsigned int timer_clk;

static bool timer25Mhz = true;

static u32 enable_mask;

​

/*

 * Number of timer ticks per jiffy.

 */

static u32 ticks_per_jiffy;

​

static struct clock_event_device __percpu *armada_370_xp_evt;

​

static void local_timer_ctrl_clrset(u32 clr, u32 set)

{