linux-imx

/*

 * System timer for CSR SiRFprimaII

 *

 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.

 *

 * Licensed under GPLv2 or later.

 */

​

#include <linux/kernel.h>

#include <linux/interrupt.h>

#include <linux/clockchips.h>

#include <linux/clocksource.h>

#include <linux/cpu.h>

#include <linux/bitops.h>

#include <linux/irq.h>

#include <linux/clk.h>

#include <linux/slab.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/of_address.h>

#include <linux/sched_clock.h>

​

#define SIRFSOC_TIMER_32COUNTER_0_CTRL          0x0000

#define SIRFSOC_TIMER_32COUNTER_1_CTRL          0x0004

#define SIRFSOC_TIMER_MATCH_0               0x0018

#define SIRFSOC_TIMER_MATCH_1               0x001c

#define SIRFSOC_TIMER_COUNTER_0             0x0048

#define SIRFSOC_TIMER_COUNTER_1             0x004c

#define SIRFSOC_TIMER_INTR_STATUS           0x0060

#define SIRFSOC_TIMER_WATCHDOG_EN           0x0064

#define SIRFSOC_TIMER_64COUNTER_CTRL            0x0068

#define SIRFSOC_TIMER_64COUNTER_LO          0x006c

#define SIRFSOC_TIMER_64COUNTER_HI          0x0070

#define SIRFSOC_TIMER_64COUNTER_LOAD_LO         0x0074

#define SIRFSOC_TIMER_64COUNTER_LOAD_HI         0x0078

#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO     0x007c

#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI     0x0080

​

#define SIRFSOC_TIMER_REG_CNT 6

​

static unsigned long atlas7_timer_rate;

​

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {

    SIRFSOC_TIMER_WATCHDOG_EN,

    SIRFSOC_TIMER_32COUNTER_0_CTRL,

    SIRFSOC_TIMER_32COUNTER_1_CTRL,

    SIRFSOC_TIMER_64COUNTER_CTRL,

    SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,

    SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,

};

​

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

​

static void __iomem *sirfsoc_timer_base;

​

/* disable count and interrupt */

static inline void sirfsoc_timer_count_disable(int idx)

{

    writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,

        sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);

}

​

/* enable count and interrupt */

static inline void sirfsoc_timer_count_enable(int idx)

{

    writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,

        sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);

}

​

/* timer interrupt handler */

static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)

{

    struct clock_event_device *ce = dev_id;

    int cpu = smp_processor_id();

​

    /* clear timer interrupt */

    writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

​

    if (clockevent_state_oneshot(ce))

        sirfsoc_timer_count_disable(cpu);

​

    ce->event_handler(ce);

​

    return IRQ_HANDLED;

}

​

/* read 64-bit timer counter */

static u64 sirfsoc_timer_read(struct clocksource *cs)

{

    u64 cycles;

​

    writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |