linux-imx

// SPDX-License-Identifier: GPL-2.0+

//

//  Copyright (C) 2000-2001 Deep Blue Solutions

//  Copyright (C) 2002 Shane Nay (shane@minirl.com)

//  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)

//  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)

​

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/clockchips.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/sched_clock.h>

#include <linux/slab.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <soc/imx/timer.h>

​

/*

 * There are 4 versions of the timer hardware on Freescale MXC hardware.

 *  - MX1/MXL

 *  - MX21, MX27.

 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)

 *  - MX6DL, MX6SX, MX6Q(rev1.1+)

 */

​

/* defines common for all i.MX */

#define MXC_TCTL        0x00

#define MXC_TCTL_TEN        (1 << 0) /* Enable module */

#define MXC_TPRER       0x04

​

/* MX1, MX21, MX27 */

#define MX1_2_TCTL_CLK_PCLK1    (1 << 1)

#define MX1_2_TCTL_IRQEN    (1 << 4)

#define MX1_2_TCTL_FRR      (1 << 8)

#define MX1_2_TCMP      0x08

#define MX1_2_TCN       0x10

#define MX1_2_TSTAT     0x14

​

/* MX21, MX27 */

#define MX2_TSTAT_CAPT      (1 << 1)

#define MX2_TSTAT_COMP      (1 << 0)

​

/* MX31, MX35, MX25, MX5, MX6 */

#define V2_TCTL_WAITEN      (1 << 3) /* Wait enable mode */

#define V2_TCTL_CLK_IPG     (1 << 6)

#define V2_TCTL_CLK_PER     (2 << 6)

#define V2_TCTL_CLK_OSC_DIV8    (5 << 6)

#define V2_TCTL_FRR     (1 << 9)

#define V2_TCTL_24MEN       (1 << 10)

#define V2_TPRER_PRE24M     12

#define V2_IR           0x0c

#define V2_TSTAT        0x08

#define V2_TSTAT_OF1        (1 << 0)

#define V2_TCN          0x24

#define V2_TCMP         0x10

​

#define V2_TIMER_RATE_OSC_DIV8  3000000

​

struct imx_timer {

    enum imx_gpt_type type;

    void __iomem *base;

    int irq;

    struct clk *clk_per;

    struct clk *clk_ipg;

    const struct imx_gpt_data *gpt;

    struct clock_event_device ced;

    struct irqaction act;

};

​

struct imx_gpt_data {

    int reg_tstat;

    int reg_tcn;

    int reg_tcmp;

    void (*gpt_setup_tctl)(struct imx_timer *imxtm);

    void (*gpt_irq_enable)(struct imx_timer *imxtm);

    void (*gpt_irq_disable)(struct imx_timer *imxtm);

    void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);

    int (*set_next_event)(unsigned long evt,

                  struct clock_event_device *ced);

};

​

static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)

{

    return container_of(ced, struct imx_timer, ced);

}

​

static void imx1_gpt_irq_disable(struct imx_timer *imxtm)

{

    unsigned int tmp;