linux-imx

/*

 * Allwinner A1X SoCs timer handling.

 *

 * Copyright (C) 2012 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * Based on code from

 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>

 * Benn Huang <benn@allwinnertech.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

​

#include <linux/clk.h>

#include <linux/clockchips.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/irqreturn.h>

#include <linux/sched_clock.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

​

#include "timer-of.h"

​

#define TIMER_IRQ_EN_REG    0x00

#define TIMER_IRQ_EN(val)       BIT(val)

#define TIMER_IRQ_ST_REG    0x04

#define TIMER_CTL_REG(val)  (0x10 * val + 0x10)

#define TIMER_CTL_ENABLE        BIT(0)

#define TIMER_CTL_RELOAD        BIT(1)

#define TIMER_CTL_CLK_SRC(val)      (((val) & 0x3) << 2)

#define TIMER_CTL_CLK_SRC_OSC24M        (1)

#define TIMER_CTL_CLK_PRES(val)     (((val) & 0x7) << 4)

#define TIMER_CTL_ONESHOT       BIT(7)

#define TIMER_INTVAL_REG(val)   (0x10 * (val) + 0x14)

#define TIMER_CNTVAL_REG(val)   (0x10 * (val) + 0x18)

​

#define TIMER_SYNC_TICKS    3

​

/*

 * When we disable a timer, we need to wait at least for 2 cycles of

 * the timer source clock. We will use for that the clocksource timer

 * that is already setup and runs at the same frequency than the other

 * timers, and we never will be disabled.

 */

static void sun4i_clkevt_sync(void __iomem *base)

{

    u32 old = readl(base + TIMER_CNTVAL_REG(1));

​

    while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)

        cpu_relax();

}

​

static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)

{

    u32 val = readl(base + TIMER_CTL_REG(timer));

    writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));

    sun4i_clkevt_sync(base);

}

​

static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,

                    unsigned long delay)

{

    writel(delay, base + TIMER_INTVAL_REG(timer));

}

​

static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,

                    bool periodic)

{

    u32 val = readl(base + TIMER_CTL_REG(timer));

​

    if (periodic)

        val &= ~TIMER_CTL_ONESHOT;

    else

        val |= TIMER_CTL_ONESHOT;

​

    writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,

           base + TIMER_CTL_REG(timer));

}

​

static int sun4i_clkevt_shutdown(struct clock_event_device *evt)

{

    struct timer_of *to = to_timer_of(evt);

​

    sun4i_clkevt_time_stop(timer_of_base(to), 0);

​

    return 0;

}