linux-imx

/*

 * Allwinner SoCs hstimer driver.

 *

 * Copyright (C) 2013 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

​

#include <linux/clk.h>

#include <linux/clockchips.h>

#include <linux/clocksource.h>

#include <linux/delay.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/irqreturn.h>

#include <linux/reset.h>

#include <linux/slab.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

​

#define TIMER_IRQ_EN_REG        0x00

#define TIMER_IRQ_EN(val)           BIT(val)

#define TIMER_IRQ_ST_REG        0x04

#define TIMER_CTL_REG(val)      (0x20 * (val) + 0x10)

#define TIMER_CTL_ENABLE            BIT(0)

#define TIMER_CTL_RELOAD            BIT(1)

#define TIMER_CTL_CLK_PRES(val)         (((val) & 0x7) << 4)

#define TIMER_CTL_ONESHOT           BIT(7)

#define TIMER_INTVAL_LO_REG(val)    (0x20 * (val) + 0x14)

#define TIMER_INTVAL_HI_REG(val)    (0x20 * (val) + 0x18)

#define TIMER_CNTVAL_LO_REG(val)    (0x20 * (val) + 0x1c)

#define TIMER_CNTVAL_HI_REG(val)    (0x20 * (val) + 0x20)

​

#define TIMER_SYNC_TICKS    3

​

struct sun5i_timer {

    void __iomem        *base;

    struct clk      *clk;

    struct notifier_block   clk_rate_cb;

    u32         ticks_per_jiffy;

};

​

#define to_sun5i_timer(x) \

    container_of(x, struct sun5i_timer, clk_rate_cb)

​

struct sun5i_timer_clksrc {

    struct sun5i_timer  timer;

    struct clocksource  clksrc;

};

​

#define to_sun5i_timer_clksrc(x) \

    container_of(x, struct sun5i_timer_clksrc, clksrc)

​

struct sun5i_timer_clkevt {

    struct sun5i_timer      timer;

    struct clock_event_device   clkevt;

};

​

#define to_sun5i_timer_clkevt(x) \

    container_of(x, struct sun5i_timer_clkevt, clkevt)

​

/*

 * When we disable a timer, we need to wait at least for 2 cycles of

 * the timer source clock. We will use for that the clocksource timer

 * that is already setup and runs at the same frequency than the other

 * timers, and we never will be disabled.

 */

static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)

{

    u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));

​

    while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)

        cpu_relax();

}

​

static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)

{

    u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));

    writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));

​

    sun5i_clkevt_sync(ce);

}

​

static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)

{

    writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));

}