linux-imx

/*

 * Copyright (C) 2007-2009 ST-Ericsson AB

 * License terms: GNU General Public License (GPL) version 2

 * Timer COH 901 328, runs the OS timer interrupt.

 * Author: Linus Walleij <linus.walleij@stericsson.com>

 */

#include <linux/interrupt.h>

#include <linux/time.h>

#include <linux/timex.h>

#include <linux/clockchips.h>

#include <linux/clocksource.h>

#include <linux/types.h>

#include <linux/io.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/irq.h>

#include <linux/delay.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/sched_clock.h>

​

/* Generic stuff */

#include <asm/mach/map.h>

#include <asm/mach/time.h>

​

/*

 * APP side special timer registers

 * This timer contains four timers which can fire an interrupt each.

 * OS (operating system) timer @ 32768 Hz

 * DD (device driver) timer @ 1 kHz

 * GP1 (general purpose 1) timer @ 1MHz

 * GP2 (general purpose 2) timer @ 1MHz

 */

​

/* Reset OS Timer 32bit (-/W) */

#define U300_TIMER_APP_ROST                 (0x0000)

#define U300_TIMER_APP_ROST_TIMER_RESET             (0x00000000)

/* Enable OS Timer 32bit (-/W) */

#define U300_TIMER_APP_EOST                 (0x0004)

#define U300_TIMER_APP_EOST_TIMER_ENABLE            (0x00000000)

/* Disable OS Timer 32bit (-/W) */

#define U300_TIMER_APP_DOST                 (0x0008)

#define U300_TIMER_APP_DOST_TIMER_DISABLE           (0x00000000)

/* OS Timer Mode Register 32bit (-/W) */

#define U300_TIMER_APP_SOSTM                    (0x000c)

#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS            (0x00000000)

#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT          (0x00000001)

/* OS Timer Status Register 32bit (R/-) */

#define U300_TIMER_APP_OSTS                 (0x0010)

#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK            (0x0000000F)

#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE            (0x00000001)

#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE          (0x00000002)

#define U300_TIMER_APP_OSTS_ENABLE_IND              (0x00000010)

#define U300_TIMER_APP_OSTS_MODE_MASK               (0x00000020)

#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS         (0x00000000)

#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT           (0x00000020)

#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND         (0x00000040)

#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND         (0x00000080)

/* OS Timer Current Count Register 32bit (R/-) */

#define U300_TIMER_APP_OSTCC                    (0x0014)

/* OS Timer Terminal Count Register 32bit (R/W) */

#define U300_TIMER_APP_OSTTC                    (0x0018)

/* OS Timer Interrupt Enable Register 32bit (-/W) */