linux-imx

// SPDX-License-Identifier: GPL-2.0+

/*

 * CPU frequency scaling support for Armada 37xx platform.

 *

 * Copyright (C) 2017 Marvell

 *

 * Gregory CLEMENT <gregory.clement@free-electrons.com>

 */

​

#include <linux/clk.h>

#include <linux/cpu.h>

#include <linux/cpufreq.h>

#include <linux/err.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/pm_opp.h>

#include <linux/regmap.h>

#include <linux/slab.h>

​

#include "cpufreq-dt.h"

​

/* Power management in North Bridge register set */

#define ARMADA_37XX_NB_L0L1 0x18

#define ARMADA_37XX_NB_L2L3 0x1C

#define  ARMADA_37XX_NB_TBG_DIV_OFF 13

#define  ARMADA_37XX_NB_TBG_DIV_MASK    0x7

#define  ARMADA_37XX_NB_CLK_SEL_OFF 11

#define  ARMADA_37XX_NB_CLK_SEL_MASK    0x1

#define  ARMADA_37XX_NB_CLK_SEL_TBG 0x1

#define  ARMADA_37XX_NB_TBG_SEL_OFF 9

#define  ARMADA_37XX_NB_TBG_SEL_MASK    0x3

#define  ARMADA_37XX_NB_VDD_SEL_OFF 6

#define  ARMADA_37XX_NB_VDD_SEL_MASK    0x3

#define  ARMADA_37XX_NB_CONFIG_SHIFT    16

#define ARMADA_37XX_NB_DYN_MOD  0x24

#define  ARMADA_37XX_NB_CLK_SEL_EN  BIT(26)

#define  ARMADA_37XX_NB_TBG_EN      BIT(28)

#define  ARMADA_37XX_NB_DIV_EN      BIT(29)

#define  ARMADA_37XX_NB_VDD_EN      BIT(30)

#define  ARMADA_37XX_NB_DFS_EN      BIT(31)

#define ARMADA_37XX_NB_CPU_LOAD 0x30

#define  ARMADA_37XX_NB_CPU_LOAD_MASK   0x3

#define  ARMADA_37XX_DVFS_LOAD_0    0

#define  ARMADA_37XX_DVFS_LOAD_1    1

#define  ARMADA_37XX_DVFS_LOAD_2    2

#define  ARMADA_37XX_DVFS_LOAD_3    3

​

/* AVS register set */

#define ARMADA_37XX_AVS_CTL0        0x0

#define  ARMADA_37XX_AVS_ENABLE     BIT(30)

#define  ARMADA_37XX_AVS_HIGH_VDD_LIMIT 16

#define  ARMADA_37XX_AVS_LOW_VDD_LIMIT  22

#define  ARMADA_37XX_AVS_VDD_MASK   0x3F

#define ARMADA_37XX_AVS_CTL2        0x8

#define  ARMADA_37XX_AVS_LOW_VDD_EN BIT(6)

#define ARMADA_37XX_AVS_VSET(x)     (0x1C + 4 * (x))

​

/*

 * On Armada 37xx the Power management manages 4 level of CPU load,

 * each level can be associated with a CPU clock source, a CPU

 * divider, a VDD level, etc...

 */

#define LOAD_LEVEL_NR   4

​

#define MIN_VOLT_MV 1000

​

/*  AVS value for the corresponding voltage (in mV) */

static int avs_map[] = {

    747, 758, 770, 782, 793, 805, 817, 828, 840, 852, 863, 875, 887, 898,

    910, 922, 933, 945, 957, 968, 980, 992, 1003, 1015, 1027, 1038, 1050,

    1062, 1073, 1085, 1097, 1108, 1120, 1132, 1143, 1155, 1167, 1178, 1190,

    1202, 1213, 1225, 1237, 1248, 1260, 1272, 1283, 1295, 1307, 1318, 1330,

    1342

};

​

struct armada37xx_cpufreq_state {

    struct regmap *regmap;

    u32 nb_l0l1;

    u32 nb_l2l3;

    u32 nb_dyn_mod;

    u32 nb_cpu_load;

};

​

static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state;

​

struct armada_37xx_dvfs {