linux-imx

/* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support

 *

 * Copyright (C) 2003 David S. Miller (davem@redhat.com)

 *

 * Many thanks to Dominik Brodowski for fixing up the cpufreq

 * infrastructure in order to make this driver easier to implement.

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/sched.h>

#include <linux/smp.h>

#include <linux/cpufreq.h>

#include <linux/threads.h>

#include <linux/slab.h>

#include <linux/delay.h>

#include <linux/init.h>

​

#include <asm/asi.h>

#include <asm/timer.h>

​

static struct cpufreq_driver *cpufreq_us2e_driver;

​

struct us2e_freq_percpu_info {

    struct cpufreq_frequency_table table[6];

};

​

/* Indexed by cpu number. */

static struct us2e_freq_percpu_info *us2e_freq_table;

​

#define HBIRD_MEM_CNTL0_ADDR    0x1fe0000f010UL

#define HBIRD_ESTAR_MODE_ADDR   0x1fe0000f080UL

​

/* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8.  These are controlled

 * in the ESTAR mode control register.

 */

#define ESTAR_MODE_DIV_1    0x0000000000000000UL

#define ESTAR_MODE_DIV_2    0x0000000000000001UL

#define ESTAR_MODE_DIV_4    0x0000000000000003UL

#define ESTAR_MODE_DIV_6    0x0000000000000002UL

#define ESTAR_MODE_DIV_8    0x0000000000000004UL

#define ESTAR_MODE_DIV_MASK 0x0000000000000007UL

​

#define MCTRL0_SREFRESH_ENAB    0x0000000000010000UL

#define MCTRL0_REFR_COUNT_MASK  0x0000000000007f00UL

#define MCTRL0_REFR_COUNT_SHIFT 8

#define MCTRL0_REFR_INTERVAL    7800

#define MCTRL0_REFR_CLKS_P_CNT  64

​

static unsigned long read_hbreg(unsigned long addr)

{

    unsigned long ret;

​

    __asm__ __volatile__("ldxa  [%1] %2, %0"

                 : "=&r" (ret)

                 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

    return ret;

}

​

static void write_hbreg(unsigned long addr, unsigned long val)

{

    __asm__ __volatile__("stxa  %0, [%1] %2\n\t"

                 "membar    #Sync"

                 : /* no outputs */

                 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)

                 : "memory");

    if (addr == HBIRD_ESTAR_MODE_ADDR) {

        /* Need to wait 16 clock cycles for the PLL to lock.  */

        udelay(1);

    }

}

​

static void self_refresh_ctl(int enable)

{

    unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);

​

    if (enable)

        mctrl |= MCTRL0_SREFRESH_ENAB;

    else

        mctrl &= ~MCTRL0_SREFRESH_ENAB;

    write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);

    (void) read_hbreg(HBIRD_MEM_CNTL0_ADDR);

}

​

static void frob_mem_refresh(int cpu_slowing_down,

                 unsigned long clock_tick,

                 unsigned long old_divisor, unsigned long divisor)

{

    unsigned long old_refr_count, refr_count, mctrl;

​

    refr_count  = (clock_tick * MCTRL0_REFR_INTERVAL);

    refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL);