linux-imx

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright 2015-2016 Freescale Semiconductor Inc.

 * Copyright 2017-2018 NXP

 */

​

#include "compat.h"

#include "regs.h"

#include "caamalg_qi2.h"

#include "dpseci_cmd.h"

#include "desc_constr.h"

#include "error.h"

#include "sg_sw_sec4.h"

#include "sg_sw_qm2.h"

#include "key_gen.h"

#include "caamalg_desc.h"

#include "caamhash_desc.h"

#include <linux/fsl/mc.h>

#include <soc/fsl/dpaa2-io.h>

#include <soc/fsl/dpaa2-fd.h>

​

#define CAAM_CRA_PRIORITY   2000

​

/* max key is sum of AES_MAX_KEY_SIZE, max split key size */

#define CAAM_MAX_KEY_SIZE   (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \

                 SHA512_DIGEST_SIZE * 2)

​

/*

 * This is a a cache of buffers, from which the users of CAAM QI driver

 * can allocate short buffers. It's speedier than doing kmalloc on the hotpath.

 * NOTE: A more elegant solution would be to have some headroom in the frames

 *       being processed. This can be added by the dpaa2-eth driver. This would

 *       pose a problem for userspace application processing which cannot

 *       know of this limitation. So for now, this will work.

 * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here

 */

static struct kmem_cache *qi_cache;

​

struct caam_alg_entry {

    struct device *dev;

    int class1_alg_type;

    int class2_alg_type;

    bool rfc3686;

    bool geniv;

};

​

struct caam_aead_alg {

    struct aead_alg aead;

    struct caam_alg_entry caam;

    bool registered;

};

​

struct caam_skcipher_alg {

    struct skcipher_alg skcipher;

    struct caam_alg_entry caam;

    bool registered;

};

​

/**

 * caam_ctx - per-session context

 * @flc: Flow Contexts array

 * @key:  [authentication key], encryption key

 * @flc_dma: I/O virtual addresses of the Flow Contexts

 * @key_dma: I/O virtual address of the key

 * @dir: DMA direction for mapping key and Flow Contexts

 * @dev: dpseci device

 * @adata: authentication algorithm details

 * @cdata: encryption algorithm details

 * @authsize: authentication tag (a.k.a. ICV / MAC) size

 */

struct caam_ctx {

    struct caam_flc flc[NUM_OP];

    u8 key[CAAM_MAX_KEY_SIZE];

    dma_addr_t flc_dma[NUM_OP];

    dma_addr_t key_dma;

    enum dma_data_direction dir;

    struct device *dev;

    struct alginfo adata;

    struct alginfo cdata;

    unsigned int authsize;

};

​

static void *dpaa2_caam_iova_to_virt(struct dpaa2_caam_priv *priv,

                     dma_addr_t iova_addr)

{

    phys_addr_t phys_addr;

​

    phys_addr = priv->domain ? iommu_iova_to_phys(priv->domain, iova_addr) :

                   iova_addr;

​

    return phys_to_virt(phys_addr);

}