linux-imx

// SPDX-License-Identifier: GPL-2.0

/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <crypto/algapi.h>

#include <crypto/hash.h>

#include <crypto/md5.h>

#include <crypto/sm3.h>

#include <crypto/internal/hash.h>

​

#include "cc_driver.h"

#include "cc_request_mgr.h"

#include "cc_buffer_mgr.h"

#include "cc_hash.h"

#include "cc_sram_mgr.h"

​

#define CC_MAX_HASH_SEQ_LEN 12

#define CC_MAX_OPAD_KEYS_SIZE CC_MAX_HASH_BLCK_SIZE

#define CC_SM3_HASH_LEN_SIZE 8

​

struct cc_hash_handle {

    cc_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/

    cc_sram_addr_t larval_digest_sram_addr;   /* const value in SRAM */

    struct list_head hash_list;

};

​

static const u32 digest_len_init[] = {

    0x00000040, 0x00000000, 0x00000000, 0x00000000 };

static const u32 md5_init[] = {

    SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };

static const u32 sha1_init[] = {

    SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };

static const u32 sha224_init[] = {

    SHA224_H7, SHA224_H6, SHA224_H5, SHA224_H4,

    SHA224_H3, SHA224_H2, SHA224_H1, SHA224_H0 };

static const u32 sha256_init[] = {

    SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4,

    SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 };

static const u32 digest_len_sha512_init[] = {

    0x00000080, 0x00000000, 0x00000000, 0x00000000 };

static u64 sha384_init[] = {

    SHA384_H7, SHA384_H6, SHA384_H5, SHA384_H4,

    SHA384_H3, SHA384_H2, SHA384_H1, SHA384_H0 };

static u64 sha512_init[] = {

    SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4,

    SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 };

static const u32 sm3_init[] = {

    SM3_IVH, SM3_IVG, SM3_IVF, SM3_IVE,

    SM3_IVD, SM3_IVC, SM3_IVB, SM3_IVA };

​

static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],

              unsigned int *seq_size);

​

static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[],

              unsigned int *seq_size);

​

static const void *cc_larval_digest(struct device *dev, u32 mode);

​

struct cc_hash_alg {

    struct list_head entry;

    int hash_mode;

    int hw_mode;

    int inter_digestsize;

    struct cc_drvdata *drvdata;

    struct ahash_alg ahash_alg;

};

​

struct hash_key_req_ctx {

    u32 keylen;

    dma_addr_t key_dma_addr;

};

​

/* hash per-session context */

struct cc_hash_ctx {

    struct cc_drvdata *drvdata;

    /* holds the origin digest; the digest after "setkey" if HMAC,*

     * the initial digest if HASH.

     */

    u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE]  ____cacheline_aligned;

    u8 opad_tmp_keys_buff[CC_MAX_OPAD_KEYS_SIZE]  ____cacheline_aligned;

​

    dma_addr_t opad_tmp_keys_dma_addr  ____cacheline_aligned;

    dma_addr_t digest_buff_dma_addr;

    /* use for hmac with key large then mode block size */

    struct hash_key_req_ctx key_params;

    int hash_mode;

    int hw_mode;

    int inter_digestsize;

    unsigned int hash_len;

    struct completion setkey_comp;

    bool is_hmac;