linux-imx

/*

 * This file is part of STM32 Crypto driver for Linux.

 *

 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved

 * Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics.

 *

 * License terms: GPL V2.0.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more

 * details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program. If not, see <http://www.gnu.org/licenses/>.

 *

 */

​

#include <linux/clk.h>

#include <linux/crypto.h>

#include <linux/delay.h>

#include <linux/dmaengine.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/reset.h>

​

#include <crypto/engine.h>

#include <crypto/hash.h>

#include <crypto/md5.h>

#include <crypto/scatterwalk.h>

#include <crypto/sha.h>

#include <crypto/internal/hash.h>

​

#define HASH_CR             0x00

#define HASH_DIN            0x04

#define HASH_STR            0x08

#define HASH_IMR            0x20

#define HASH_SR             0x24

#define HASH_CSR(x)         (0x0F8 + ((x) * 0x04))

#define HASH_HREG(x)            (0x310 + ((x) * 0x04))

#define HASH_HWCFGR         0x3F0

#define HASH_VER            0x3F4

#define HASH_ID             0x3F8

​

/* Control Register */

#define HASH_CR_INIT            BIT(2)

#define HASH_CR_DMAE            BIT(3)

#define HASH_CR_DATATYPE_POS        4

#define HASH_CR_MODE            BIT(6)

#define HASH_CR_MDMAT           BIT(13)

#define HASH_CR_DMAA            BIT(14)

#define HASH_CR_LKEY            BIT(16)

​

#define HASH_CR_ALGO_SHA1       0x0

#define HASH_CR_ALGO_MD5        0x80

#define HASH_CR_ALGO_SHA224     0x40000

#define HASH_CR_ALGO_SHA256     0x40080

​

/* Interrupt */

#define HASH_DINIE          BIT(0)

#define HASH_DCIE           BIT(1)

​

/* Interrupt Mask */

#define HASH_MASK_CALC_COMPLETION   BIT(0)

#define HASH_MASK_DATA_INPUT        BIT(1)

​

/* Context swap register */

#define HASH_CSR_REGISTER_NUMBER    53

​

/* Status Flags */

#define HASH_SR_DATA_INPUT_READY    BIT(0)

#define HASH_SR_OUTPUT_READY        BIT(1)

#define HASH_SR_DMA_ACTIVE      BIT(2)

#define HASH_SR_BUSY            BIT(3)

​

/* STR Register */

#define HASH_STR_NBLW_MASK      GENMASK(4, 0)

#define HASH_STR_DCAL           BIT(8)

​

#define HASH_FLAGS_INIT         BIT(0)

#define HASH_FLAGS_OUTPUT_READY     BIT(1)

#define HASH_FLAGS_CPU          BIT(2)