linux-imx

/*

 * Header file for the Atmel AHB DMA Controller driver

 *

 * Copyright (C) 2008 Atmel Corporation

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef AT_HDMAC_REGS_H

#define AT_HDMAC_REGS_H

​

#include <linux/platform_data/dma-atmel.h>

​

#define AT_DMA_MAX_NR_CHANNELS  8

​

​

#define AT_DMA_GCFG 0x00    /* Global Configuration Register */

#define     AT_DMA_IF_BIGEND(i) (0x1 << (i))    /* AHB-Lite Interface i in Big-endian mode */

#define     AT_DMA_ARB_CFG  (0x1 << 4)  /* Arbiter mode. */

#define         AT_DMA_ARB_CFG_FIXED        (0x0 << 4)

#define         AT_DMA_ARB_CFG_ROUND_ROBIN  (0x1 << 4)

​

#define AT_DMA_EN   0x04    /* Controller Enable Register */

#define     AT_DMA_ENABLE   (0x1 << 0)

​

#define AT_DMA_SREQ 0x08    /* Software Single Request Register */

#define     AT_DMA_SSREQ(x) (0x1 << ((x) << 1))     /* Request a source single transfer on channel x */

#define     AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1)))   /* Request a destination single transfer on channel x */

​

#define AT_DMA_CREQ 0x0C    /* Software Chunk Transfer Request Register */

#define     AT_DMA_SCREQ(x) (0x1 << ((x) << 1))     /* Request a source chunk transfer on channel x */

#define     AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1)))   /* Request a destination chunk transfer on channel x */

​

#define AT_DMA_LAST 0x10    /* Software Last Transfer Flag Register */

#define     AT_DMA_SLAST(x) (0x1 << ((x) << 1))     /* This src rq is last tx of buffer on channel x */

#define     AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1)))   /* This dst rq is last tx of buffer on channel x */

​

#define AT_DMA_SYNC 0x14    /* Request Synchronization Register */

#define     AT_DMA_SYR(h)   (0x1 << (h))            /* Synchronize handshake line h */

​

/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */

#define AT_DMA_EBCIER   0x18    /* Enable register */

#define AT_DMA_EBCIDR   0x1C    /* Disable register */

#define AT_DMA_EBCIMR   0x20    /* Mask Register */

#define AT_DMA_EBCISR   0x24    /* Status Register */

#define     AT_DMA_CBTC_OFFSET  8

#define     AT_DMA_ERR_OFFSET   16

#define     AT_DMA_BTC(x)   (0x1 << (x))

#define     AT_DMA_CBTC(x)  (0x1 << (AT_DMA_CBTC_OFFSET + (x)))

#define     AT_DMA_ERR(x)   (0x1 << (AT_DMA_ERR_OFFSET + (x)))

​

#define AT_DMA_CHER 0x28    /* Channel Handler Enable Register */

#define     AT_DMA_ENA(x)   (0x1 << (x))

#define     AT_DMA_SUSP(x)  (0x1 << ( 8 + (x)))

#define     AT_DMA_KEEP(x)  (0x1 << (24 + (x)))

​

#define AT_DMA_CHDR 0x2C    /* Channel Handler Disable Register */

#define     AT_DMA_DIS(x)   (0x1 << (x))

#define     AT_DMA_RES(x)   (0x1 << ( 8 + (x)))

​

#define AT_DMA_CHSR 0x30    /* Channel Handler Status Register */

#define     AT_DMA_EMPT(x)  (0x1 << (16 + (x)))

#define     AT_DMA_STAL(x)  (0x1 << (24 + (x)))

​

​

#define AT_DMA_CH_REGS_BASE 0x3C    /* Channel registers base address */

#define ch_regs(x)  (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */

​

/* Hardware register offset for each channel */

#define ATC_SADDR_OFFSET    0x00    /* Source Address Register */

#define ATC_DADDR_OFFSET    0x04    /* Destination Address Register */

#define ATC_DSCR_OFFSET     0x08    /* Descriptor Address Register */

#define ATC_CTRLA_OFFSET    0x0C    /* Control A Register */

#define ATC_CTRLB_OFFSET    0x10    /* Control B Register */

#define ATC_CFG_OFFSET      0x14    /* Configuration Register */

#define ATC_SPIP_OFFSET     0x18    /* Src PIP Configuration Register */

#define ATC_DPIP_OFFSET     0x1C    /* Dst PIP Configuration Register */

​

​

/* Bitfield definitions */

​

/* Bitfields in DSCR */

#define ATC_DSCR_IF(i)      (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */

​

/* Bitfields in CTRLA */

#define ATC_BTSIZE_MAX      0xFFFFUL    /* Maximum Buffer Transfer Size */

#define ATC_BTSIZE(x)       (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */

#define ATC_SCSIZE_MASK     (0x7 << 16) /* Source Chunk Transfer Size */

#define     ATC_SCSIZE(x)       (ATC_SCSIZE_MASK & ((x) << 16))

#define     ATC_SCSIZE_1        (0x0 << 16)