linux-imx

/*

 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)

 *

 * Copyright (C) 2014 Atmel Corporation

 *

 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

​

#include <asm/barrier.h>

#include <dt-bindings/dma/at91.h>

#include <linux/clk.h>

#include <linux/dmaengine.h>

#include <linux/dmapool.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/kernel.h>

#include <linux/list.h>

#include <linux/module.h>

#include <linux/of_dma.h>

#include <linux/of_platform.h>

#include <linux/platform_device.h>

#include <linux/pm.h>

​

#include "dmaengine.h"

​

/* Global registers */

#define AT_XDMAC_GTYPE      0x00    /* Global Type Register */

#define     AT_XDMAC_NB_CH(i)   (((i) & 0x1F) + 1)      /* Number of Channels Minus One */

#define     AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF)        /* Number of Bytes */

#define     AT_XDMAC_NB_REQ(i)  ((((i) >> 16) & 0x3F) + 1)  /* Number of Peripheral Requests Minus One */

#define AT_XDMAC_GCFG       0x04    /* Global Configuration Register */

#define AT_XDMAC_GWAC       0x08    /* Global Weighted Arbiter Configuration Register */

#define AT_XDMAC_GIE        0x0C    /* Global Interrupt Enable Register */

#define AT_XDMAC_GID        0x10    /* Global Interrupt Disable Register */

#define AT_XDMAC_GIM        0x14    /* Global Interrupt Mask Register */

#define AT_XDMAC_GIS        0x18    /* Global Interrupt Status Register */

#define AT_XDMAC_GE     0x1C    /* Global Channel Enable Register */

#define AT_XDMAC_GD     0x20    /* Global Channel Disable Register */

#define AT_XDMAC_GS     0x24    /* Global Channel Status Register */

#define AT_XDMAC_GRS        0x28    /* Global Channel Read Suspend Register */

#define AT_XDMAC_GWS        0x2C    /* Global Write Suspend Register */

#define AT_XDMAC_GRWS       0x30    /* Global Channel Read Write Suspend Register */

#define AT_XDMAC_GRWR       0x34    /* Global Channel Read Write Resume Register */

#define AT_XDMAC_GSWR       0x38    /* Global Channel Software Request Register */

#define AT_XDMAC_GSWS       0x3C    /* Global channel Software Request Status Register */

#define AT_XDMAC_GSWF       0x40    /* Global Channel Software Flush Request Register */

#define AT_XDMAC_VERSION    0xFFC   /* XDMAC Version Register */

​

/* Channel relative registers offsets */

#define AT_XDMAC_CIE        0x00    /* Channel Interrupt Enable Register */

#define     AT_XDMAC_CIE_BIE    BIT(0)  /* End of Block Interrupt Enable Bit */

#define     AT_XDMAC_CIE_LIE    BIT(1)  /* End of Linked List Interrupt Enable Bit */

#define     AT_XDMAC_CIE_DIE    BIT(2)  /* End of Disable Interrupt Enable Bit */

#define     AT_XDMAC_CIE_FIE    BIT(3)  /* End of Flush Interrupt Enable Bit */

#define     AT_XDMAC_CIE_RBEIE  BIT(4)  /* Read Bus Error Interrupt Enable Bit */

#define     AT_XDMAC_CIE_WBEIE  BIT(5)  /* Write Bus Error Interrupt Enable Bit */

#define     AT_XDMAC_CIE_ROIE   BIT(6)  /* Request Overflow Interrupt Enable Bit */

#define AT_XDMAC_CID        0x04    /* Channel Interrupt Disable Register */

#define     AT_XDMAC_CID_BID    BIT(0)  /* End of Block Interrupt Disable Bit */

#define     AT_XDMAC_CID_LID    BIT(1)  /* End of Linked List Interrupt Disable Bit */

#define     AT_XDMAC_CID_DID    BIT(2)  /* End of Disable Interrupt Disable Bit */

#define     AT_XDMAC_CID_FID    BIT(3)  /* End of Flush Interrupt Disable Bit */

#define     AT_XDMAC_CID_RBEID  BIT(4)  /* Read Bus Error Interrupt Disable Bit */

#define     AT_XDMAC_CID_WBEID  BIT(5)  /* Write Bus Error Interrupt Disable Bit */

#define     AT_XDMAC_CID_ROID   BIT(6)  /* Request Overflow Interrupt Disable Bit */

#define AT_XDMAC_CIM        0x08    /* Channel Interrupt Mask Register */

#define     AT_XDMAC_CIM_BIM    BIT(0)  /* End of Block Interrupt Mask Bit */

#define     AT_XDMAC_CIM_LIM    BIT(1)  /* End of Linked List Interrupt Mask Bit */

#define     AT_XDMAC_CIM_DIM    BIT(2)  /* End of Disable Interrupt Mask Bit */

#define     AT_XDMAC_CIM_FIM    BIT(3)  /* End of Flush Interrupt Mask Bit */

#define     AT_XDMAC_CIM_RBEIM  BIT(4)  /* Read Bus Error Interrupt Mask Bit */

#define     AT_XDMAC_CIM_WBEIM  BIT(5)  /* Write Bus Error Interrupt Mask Bit */

#define     AT_XDMAC_CIM_ROIM   BIT(6)  /* Request Overflow Interrupt Mask Bit */

#define AT_XDMAC_CIS        0x0C    /* Channel Interrupt Status Register */

#define     AT_XDMAC_CIS_BIS    BIT(0)  /* End of Block Interrupt Status Bit */

#define     AT_XDMAC_CIS_LIS    BIT(1)  /* End of Linked List Interrupt Status Bit */

#define     AT_XDMAC_CIS_DIS    BIT(2)  /* End of Disable Interrupt Status Bit */

#define     AT_XDMAC_CIS_FIS    BIT(3)  /* End of Flush Interrupt Status Bit */

#define     AT_XDMAC_CIS_RBEIS  BIT(4)  /* Read Bus Error Interrupt Status Bit */

#define     AT_XDMAC_CIS_WBEIS  BIT(5)  /* Write Bus Error Interrupt Status Bit */