linux-imx

/*

 * Ingenic JZ4780 DMA controller

 *

 * Copyright (c) 2015 Imagination Technologies

 * Author: Alex Smith <alex@alex-smith.me.uk>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

​

#include <linux/clk.h>

#include <linux/dmapool.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_dma.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

​

#include "dmaengine.h"

#include "virt-dma.h"

​

/* Global registers. */

#define JZ_DMA_REG_DMAC     0x00

#define JZ_DMA_REG_DIRQP    0x04

#define JZ_DMA_REG_DDR      0x08

#define JZ_DMA_REG_DDRS     0x0c

#define JZ_DMA_REG_DCKE     0x10

#define JZ_DMA_REG_DCKES    0x14

#define JZ_DMA_REG_DCKEC    0x18

#define JZ_DMA_REG_DMACP    0x1c

#define JZ_DMA_REG_DSIRQP   0x20

#define JZ_DMA_REG_DSIRQM   0x24

#define JZ_DMA_REG_DCIRQP   0x28

#define JZ_DMA_REG_DCIRQM   0x2c

​

/* Per-channel registers. */

#define JZ_DMA_REG_CHAN(n)  (n * 0x20)

#define JZ_DMA_REG_DSA      0x00

#define JZ_DMA_REG_DTA      0x04

#define JZ_DMA_REG_DTC      0x08

#define JZ_DMA_REG_DRT      0x0c

#define JZ_DMA_REG_DCS      0x10

#define JZ_DMA_REG_DCM      0x14

#define JZ_DMA_REG_DDA      0x18

#define JZ_DMA_REG_DSD      0x1c

​

#define JZ_DMA_DMAC_DMAE    BIT(0)

#define JZ_DMA_DMAC_AR      BIT(2)

#define JZ_DMA_DMAC_HLT     BIT(3)

#define JZ_DMA_DMAC_FAIC    BIT(27)

#define JZ_DMA_DMAC_FMSC    BIT(31)

​

#define JZ_DMA_DRT_AUTO     0x8

​

#define JZ_DMA_DCS_CTE      BIT(0)

#define JZ_DMA_DCS_HLT      BIT(2)

#define JZ_DMA_DCS_TT       BIT(3)

#define JZ_DMA_DCS_AR       BIT(4)

#define JZ_DMA_DCS_DES8     BIT(30)

​

#define JZ_DMA_DCM_LINK     BIT(0)

#define JZ_DMA_DCM_TIE      BIT(1)

#define JZ_DMA_DCM_STDE     BIT(2)

#define JZ_DMA_DCM_TSZ_SHIFT    8

#define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT)

#define JZ_DMA_DCM_DP_SHIFT 12

#define JZ_DMA_DCM_SP_SHIFT 14

#define JZ_DMA_DCM_DAI      BIT(22)

#define JZ_DMA_DCM_SAI      BIT(23)

​

#define JZ_DMA_SIZE_4_BYTE  0x0

#define JZ_DMA_SIZE_1_BYTE  0x1

#define JZ_DMA_SIZE_2_BYTE  0x2

#define JZ_DMA_SIZE_16_BYTE 0x3

#define JZ_DMA_SIZE_32_BYTE 0x4

#define JZ_DMA_SIZE_64_BYTE 0x5

#define JZ_DMA_SIZE_128_BYTE    0x6

​

#define JZ_DMA_WIDTH_32_BIT 0x0

#define JZ_DMA_WIDTH_8_BIT  0x1

#define JZ_DMA_WIDTH_16_BIT 0x2

​

#define JZ_DMA_BUSWIDTHS    (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)  | \

                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \

                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))

​

#define JZ4780_DMA_CTRL_OFFSET  0x1000