linux-imx

/*

 * IMG Multi-threaded DMA Controller (MDC)

 *

 * Copyright (C) 2009,2012,2013 Imagination Technologies Ltd.

 * Copyright (C) 2014 Google, Inc.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 */

​

#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/dmaengine.h>

#include <linux/dmapool.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_dma.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/regmap.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

#include "dmaengine.h"

#include "virt-dma.h"

​

#define MDC_MAX_DMA_CHANNELS            32

​

#define MDC_GENERAL_CONFIG          0x000

#define MDC_GENERAL_CONFIG_LIST_IEN     BIT(31)

#define MDC_GENERAL_CONFIG_IEN          BIT(29)

#define MDC_GENERAL_CONFIG_LEVEL_INT        BIT(28)

#define MDC_GENERAL_CONFIG_INC_W        BIT(12)

#define MDC_GENERAL_CONFIG_INC_R        BIT(8)

#define MDC_GENERAL_CONFIG_PHYSICAL_W       BIT(7)

#define MDC_GENERAL_CONFIG_WIDTH_W_SHIFT    4

#define MDC_GENERAL_CONFIG_WIDTH_W_MASK     0x7

#define MDC_GENERAL_CONFIG_PHYSICAL_R       BIT(3)

#define MDC_GENERAL_CONFIG_WIDTH_R_SHIFT    0

#define MDC_GENERAL_CONFIG_WIDTH_R_MASK     0x7

​

#define MDC_READ_PORT_CONFIG            0x004

#define MDC_READ_PORT_CONFIG_STHREAD_SHIFT  28

#define MDC_READ_PORT_CONFIG_STHREAD_MASK   0xf

#define MDC_READ_PORT_CONFIG_RTHREAD_SHIFT  24

#define MDC_READ_PORT_CONFIG_RTHREAD_MASK   0xf

#define MDC_READ_PORT_CONFIG_WTHREAD_SHIFT  16

#define MDC_READ_PORT_CONFIG_WTHREAD_MASK   0xf

#define MDC_READ_PORT_CONFIG_BURST_SIZE_SHIFT   4

#define MDC_READ_PORT_CONFIG_BURST_SIZE_MASK    0xff

#define MDC_READ_PORT_CONFIG_DREQ_ENABLE    BIT(1)

​

#define MDC_READ_ADDRESS            0x008

​

#define MDC_WRITE_ADDRESS           0x00c

​

#define MDC_TRANSFER_SIZE           0x010

#define MDC_TRANSFER_SIZE_MASK          0xffffff

​

#define MDC_LIST_NODE_ADDRESS           0x014

​

#define MDC_CMDS_PROCESSED          0x018

#define MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT 16

#define MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK  0x3f

#define MDC_CMDS_PROCESSED_INT_ACTIVE       BIT(8)

#define MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT  0

#define MDC_CMDS_PROCESSED_CMDS_DONE_MASK   0x3f

​

#define MDC_CONTROL_AND_STATUS          0x01c

#define MDC_CONTROL_AND_STATUS_CANCEL       BIT(20)

#define MDC_CONTROL_AND_STATUS_LIST_EN      BIT(4)

#define MDC_CONTROL_AND_STATUS_EN       BIT(0)

​

#define MDC_ACTIVE_TRANSFER_SIZE        0x030

​

#define MDC_GLOBAL_CONFIG_A             0x900

#define MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_SHIFT   16

#define MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_MASK    0xff

#define MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_SHIFT      8

#define MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_MASK       0xff

#define MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_SHIFT     0

#define MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_MASK      0xff

​

struct mdc_hw_list_desc {

    u32 gen_conf;