linux-imx

// SPDX-License-Identifier: GPL-2.0+

//

// Copyright (c) 2013-2014 Freescale Semiconductor, Inc

// Copyright (c) 2017 Sysam, Angelo Dureghello  <angelo@sysam.it>

​

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/dmaengine.h>

#include <linux/platform_device.h>

#include <linux/platform_data/dma-mcf-edma.h>

​

#include "fsl-edma-common.h"

​

#define EDMA_CHANNELS       64

#define EDMA_MASK_CH(x)     ((x) & GENMASK(5, 0))

​

static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)

{

    struct fsl_edma_engine *mcf_edma = dev_id;

    struct edma_regs *regs = &mcf_edma->regs;

    unsigned int ch;

    struct fsl_edma_chan *mcf_chan;

    u64 intmap;

​

    intmap = ioread32(regs->inth);

    intmap <<= 32;

    intmap |= ioread32(regs->intl);

    if (!intmap)

        return IRQ_NONE;

​

    for (ch = 0; ch < mcf_edma->n_chans; ch++) {

        if (intmap & BIT(ch)) {

            iowrite8(EDMA_MASK_CH(ch), regs->cint);

​

            mcf_chan = &mcf_edma->chans[ch];

​

            spin_lock(&mcf_chan->vchan.lock);

            if (!mcf_chan->edesc->iscyclic) {

                list_del(&mcf_chan->edesc->vdesc.node);

                vchan_cookie_complete(&mcf_chan->edesc->vdesc);

                mcf_chan->edesc = NULL;

                mcf_chan->status = DMA_COMPLETE;

                mcf_chan->idle = true;

            } else {

                vchan_cyclic_callback(&mcf_chan->edesc->vdesc);

            }

​

            if (!mcf_chan->edesc)

                fsl_edma_xfer_desc(mcf_chan);

​

            spin_unlock(&mcf_chan->vchan.lock);

        }

    }

​

    return IRQ_HANDLED;

}

​

static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)

{

    struct fsl_edma_engine *mcf_edma = dev_id;

    struct edma_regs *regs = &mcf_edma->regs;

    unsigned int err, ch;

​

    err = ioread32(regs->errl);

    if (!err)

        return IRQ_NONE;

​

    for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {

        if (err & BIT(ch)) {

            fsl_edma_disable_request(&mcf_edma->chans[ch]);

            iowrite8(EDMA_CERR_CERR(ch), regs->cerr);

            mcf_edma->chans[ch].status = DMA_ERROR;

            mcf_edma->chans[ch].idle = true;

        }

    }

​

    err = ioread32(regs->errh);

    if (!err)

        return IRQ_NONE;

​

    for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {

        if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {

            fsl_edma_disable_request(&mcf_edma->chans[ch]);

            iowrite8(EDMA_CERR_CERR(ch), regs->cerr);

            mcf_edma->chans[ch].status = DMA_ERROR;

            mcf_edma->chans[ch].idle = true;

        }

    }

​

    return IRQ_HANDLED;

}

​