linux-imx

/*

 * Intel MIC Platform Software Stack (MPSS)

 *

 * Copyright(c) 2014 Intel Corporation.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, version 2, as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

 * General Public License for more details.

 *

 * The full GNU General Public License is included in this distribution in

 * the file called "COPYING".

 *

 * Intel MIC X100 DMA Driver.

 *

 * Adapted from IOAT dma driver.

 */

#include <linux/module.h>

#include <linux/io.h>

#include <linux/seq_file.h>

#include <linux/vmalloc.h>

​

#include "mic_x100_dma.h"

​

#define MIC_DMA_MAX_XFER_SIZE_CARD  (1 * 1024 * 1024 -\

                       MIC_DMA_ALIGN_BYTES)

#define MIC_DMA_MAX_XFER_SIZE_HOST  (1 * 1024 * 1024 >> 1)

#define MIC_DMA_DESC_TYPE_SHIFT 60

#define MIC_DMA_MEMCPY_LEN_SHIFT 46

#define MIC_DMA_STAT_INTR_SHIFT 59

​

/* high-water mark for pushing dma descriptors */

static int mic_dma_pending_level = 4;

​

/* Status descriptor is used to write a 64 bit value to a memory location */

enum mic_dma_desc_format_type {

    MIC_DMA_MEMCPY = 1,

    MIC_DMA_STATUS,

};

​

static inline u32 mic_dma_hw_ring_inc(u32 val)

{

    return (val + 1) % MIC_DMA_DESC_RX_SIZE;

}

​

static inline u32 mic_dma_hw_ring_dec(u32 val)

{

    return val ? val - 1 : MIC_DMA_DESC_RX_SIZE - 1;

}

​

static inline void mic_dma_hw_ring_inc_head(struct mic_dma_chan *ch)

{

    ch->head = mic_dma_hw_ring_inc(ch->head);

}

​

/* Prepare a memcpy desc */

static inline void mic_dma_memcpy_desc(struct mic_dma_desc *desc,

    dma_addr_t src_phys, dma_addr_t dst_phys, u64 size)

{

    u64 qw0, qw1;

​

    qw0 = src_phys;

    qw0 |= (size >> MIC_DMA_ALIGN_SHIFT) << MIC_DMA_MEMCPY_LEN_SHIFT;

    qw1 = MIC_DMA_MEMCPY;

    qw1 <<= MIC_DMA_DESC_TYPE_SHIFT;

    qw1 |= dst_phys;

    desc->qw0 = qw0;

    desc->qw1 = qw1;

}

​

/* Prepare a status desc. with @data to be written at @dst_phys */

static inline void mic_dma_prep_status_desc(struct mic_dma_desc *desc, u64 data,

    dma_addr_t dst_phys, bool generate_intr)

{

    u64 qw0, qw1;

​

    qw0 = data;

    qw1 = (u64) MIC_DMA_STATUS << MIC_DMA_DESC_TYPE_SHIFT | dst_phys;

    if (generate_intr)

        qw1 |= (1ULL << MIC_DMA_STAT_INTR_SHIFT);

    desc->qw0 = qw0;

    desc->qw1 = qw1;

}

​

static void mic_dma_cleanup(struct mic_dma_chan *ch)

{

    struct dma_async_tx_descriptor *tx;

    u32 tail;