linux-imx

/*

 * Driver For Marvell Two-channel DMA Engine

 *

 * Copyright: Marvell International Ltd.

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 */

​

#include <linux/err.h>

#include <linux/module.h>

#include <linux/init.h>

#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/dma-mapping.h>

#include <linux/slab.h>

#include <linux/dmaengine.h>

#include <linux/platform_device.h>

#include <linux/device.h>

#include <linux/platform_data/dma-mmp_tdma.h>

#include <linux/of_device.h>

#include <linux/of_dma.h>

​

#include "dmaengine.h"

​

/*

 * Two-Channel DMA registers

 */

#define TDBCR       0x00    /* Byte Count */

#define TDSAR       0x10    /* Src Addr */

#define TDDAR       0x20    /* Dst Addr */

#define TDNDPR      0x30    /* Next Desc */

#define TDCR        0x40    /* Control */

#define TDCP        0x60    /* Priority*/

#define TDCDPR      0x70    /* Current Desc */

#define TDIMR       0x80    /* Int Mask */

#define TDISR       0xa0    /* Int Status */

​

/* Two-Channel DMA Control Register */

#define TDCR_SSZ_8_BITS     (0x0 << 22) /* Sample Size */

#define TDCR_SSZ_12_BITS    (0x1 << 22)

#define TDCR_SSZ_16_BITS    (0x2 << 22)

#define TDCR_SSZ_20_BITS    (0x3 << 22)

#define TDCR_SSZ_24_BITS    (0x4 << 22)

#define TDCR_SSZ_32_BITS    (0x5 << 22)

#define TDCR_SSZ_SHIFT      (0x1 << 22)

#define TDCR_SSZ_MASK       (0x7 << 22)

#define TDCR_SSPMOD     (0x1 << 21) /* SSP MOD */

#define TDCR_ABR        (0x1 << 20) /* Channel Abort */

#define TDCR_CDE        (0x1 << 17) /* Close Desc Enable */

#define TDCR_PACKMOD        (0x1 << 16) /* Pack Mode (ADMA Only) */

#define TDCR_CHANACT        (0x1 << 14) /* Channel Active */

#define TDCR_FETCHND        (0x1 << 13) /* Fetch Next Desc */

#define TDCR_CHANEN     (0x1 << 12) /* Channel Enable */

#define TDCR_INTMODE        (0x1 << 10) /* Interrupt Mode */

#define TDCR_CHAINMOD       (0x1 << 9)  /* Chain Mode */

#define TDCR_BURSTSZ_MSK    (0x7 << 6)  /* Burst Size */

#define TDCR_BURSTSZ_4B     (0x0 << 6)

#define TDCR_BURSTSZ_8B     (0x1 << 6)

#define TDCR_BURSTSZ_16B    (0x3 << 6)

#define TDCR_BURSTSZ_32B    (0x6 << 6)