linux-imx

/*

 * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.

 * Copyright (C) Semihalf 2009

 * Copyright (C) Ilya Yanok, Emcraft Systems 2010

 * Copyright (C) Alexander Popov, Promcontroller 2014

 * Copyright (C) Mario Six, Guntermann & Drunck GmbH, 2016

 *

 * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description

 * (defines, structures and comments) was taken from MPC5121 DMA driver

 * written by Hongjun Chen <hong-jun.chen@freescale.com>.

 *

 * Approved as OSADL project by a majority of OSADL members and funded

 * by OSADL membership fees in 2009;  for details see www.osadl.org.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License as published by the Free

 * Software Foundation; either version 2 of the License, or (at your option)

 * any later version.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * The full GNU General Public License is included in this distribution in the

 * file called COPYING.

 */

​

/*

 * MPC512x and MPC8308 DMA driver. It supports memory to memory data transfers

 * (tested using dmatest module) and data transfers between memory and

 * peripheral I/O memory by means of slave scatter/gather with these

 * limitations:

 *  - chunked transfers (described by s/g lists with more than one item) are

 *     refused as long as proper support for scatter/gather is missing

 *  - transfers on MPC8308 always start from software as this SoC does not have

 *     external request lines for peripheral flow control

 *  - memory <-> I/O memory transfer chunks of sizes of 1, 2, 4, 16 (for

 *     MPC512x), and 32 bytes are supported, and, consequently, source

 *     addresses and destination addresses must be aligned accordingly;

 *     furthermore, for MPC512x SoCs, the transfer size must be aligned on

 *     (chunk size * maxburst)

 */

​

#include <linux/module.h>

#include <linux/dmaengine.h>

#include <linux/dma-mapping.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/slab.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/of_dma.h>

#include <linux/of_platform.h>

​

#include <linux/random.h>

​

#include "dmaengine.h"

​

/* Number of DMA Transfer descriptors allocated per channel */

#define MPC_DMA_DESCRIPTORS 64

​

/* Macro definitions */

#define MPC_DMA_TCD_OFFSET  0x1000

​

/*

 * Maximum channel counts for individual hardware variants

 * and the maximum channel count over all supported controllers,

 * used for data structure size

 */

#define MPC8308_DMACHAN_MAX 16

#define MPC512x_DMACHAN_MAX 64

#define MPC_DMA_CHANNELS    64

​

/* Arbitration mode of group and channel */

#define MPC_DMA_DMACR_EDCG  (1 << 31)

#define MPC_DMA_DMACR_ERGA  (1 << 3)

#define MPC_DMA_DMACR_ERCA  (1 << 2)

​

/* Error codes */

#define MPC_DMA_DMAES_VLD   (1 << 31)

#define MPC_DMA_DMAES_GPE   (1 << 15)

#define MPC_DMA_DMAES_CPE   (1 << 14)

#define MPC_DMA_DMAES_ERRCHN(err) \

                (((err) >> 8) & 0x3f)

#define MPC_DMA_DMAES_SAE   (1 << 7)

#define MPC_DMA_DMAES_SOE   (1 << 6)

#define MPC_DMA_DMAES_DAE   (1 << 5)

#define MPC_DMA_DMAES_DOE   (1 << 4)

#define MPC_DMA_DMAES_NCE   (1 << 3)

#define MPC_DMA_DMAES_SGE   (1 << 2)