linux-imx

// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * Copyright (C) 2015-2016 Marvell International Ltd.

​

 */

​

#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/msi.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/spinlock.h>

​

#include "dmaengine.h"

​

/* DMA Engine Registers */

#define MV_XOR_V2_DMA_DESQ_BALR_OFF         0x000

#define MV_XOR_V2_DMA_DESQ_BAHR_OFF         0x004

#define MV_XOR_V2_DMA_DESQ_SIZE_OFF         0x008

#define MV_XOR_V2_DMA_DESQ_DONE_OFF         0x00C

#define   MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK      0x7FFF

#define   MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT     0

#define   MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_MASK     0x1FFF

#define   MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_SHIFT    16

#define MV_XOR_V2_DMA_DESQ_ARATTR_OFF           0x010

#define   MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK        0x3F3F

#define   MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE   0x202

#define   MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE     0x3C3C

#define MV_XOR_V2_DMA_IMSG_CDAT_OFF         0x014

#define MV_XOR_V2_DMA_IMSG_THRD_OFF         0x018

#define   MV_XOR_V2_DMA_IMSG_THRD_MASK          0x7FFF

#define   MV_XOR_V2_DMA_IMSG_THRD_SHIFT         0x0

#define   MV_XOR_V2_DMA_IMSG_TIMER_EN           BIT(18)

#define MV_XOR_V2_DMA_DESQ_AWATTR_OFF           0x01C

  /* Same flags as MV_XOR_V2_DMA_DESQ_ARATTR_OFF */

#define MV_XOR_V2_DMA_DESQ_ALLOC_OFF            0x04C

#define   MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_MASK       0xFFFF

#define   MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_SHIFT      16

#define MV_XOR_V2_DMA_IMSG_BALR_OFF         0x050

#define MV_XOR_V2_DMA_IMSG_BAHR_OFF         0x054

#define MV_XOR_V2_DMA_DESQ_CTRL_OFF         0x100

#define   MV_XOR_V2_DMA_DESQ_CTRL_32B           1

#define   MV_XOR_V2_DMA_DESQ_CTRL_128B          7

#define MV_XOR_V2_DMA_DESQ_STOP_OFF         0x800

#define MV_XOR_V2_DMA_DESQ_DEALLOC_OFF          0x804

#define MV_XOR_V2_DMA_DESQ_ADD_OFF          0x808

#define MV_XOR_V2_DMA_IMSG_TMOT             0x810

#define   MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK        0x1FFF

#define   MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT       0

​

/* XOR Global registers */

#define MV_XOR_V2_GLOB_BW_CTRL              0x4

#define   MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_SHIFT  0

#define   MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_VAL    64

#define   MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_SHIFT  8

#define   MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_VAL    8

#define   MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_SHIFT 12

#define   MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_VAL   4

#define   MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_SHIFT 16

#define   MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_VAL   4

#define MV_XOR_V2_GLOB_PAUSE                0x014

#define   MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL     0x8

#define MV_XOR_V2_GLOB_SYS_INT_CAUSE            0x200

#define MV_XOR_V2_GLOB_SYS_INT_MASK         0x204

#define MV_XOR_V2_GLOB_MEM_INT_CAUSE            0x220

#define MV_XOR_V2_GLOB_MEM_INT_MASK         0x224

​

#define MV_XOR_V2_MIN_DESC_SIZE             32

#define MV_XOR_V2_EXT_DESC_SIZE             128

​

#define MV_XOR_V2_DESC_RESERVED_SIZE            12

#define MV_XOR_V2_DESC_BUFF_D_ADDR_SIZE         12

​

#define MV_XOR_V2_CMD_LINE_NUM_MAX_D_BUF        8

​

/*

 * Descriptors queue size. With 32 bytes descriptors, up to 2^14

 * descriptors are allowed, with 128 bytes descriptors, up to 2^12

 * descriptors are allowed. This driver uses 128 bytes descriptors,

 * but experimentation has shown that a set of 1024 descriptors is

 * sufficient to reach a good level of performance.

 */

#define MV_XOR_V2_DESC_NUM              1024

​

/*

 * Threshold values for descriptors and timeout, determined by

 * experimentation as giving a good level of performance.

 */