linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.

 * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>

 */

​

#include <linux/bitmap.h>

#include <linux/bitops.h>

#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/dmaengine.h>

#include <linux/err.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/log2.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_dma.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

​

#include <dt-bindings/dma/nbpfaxi.h>

​

#include "dmaengine.h"

​

#define NBPF_REG_CHAN_OFFSET    0

#define NBPF_REG_CHAN_SIZE  0x40

​

/* Channel Current Transaction Byte register */

#define NBPF_CHAN_CUR_TR_BYTE   0x20

​

/* Channel Status register */

#define NBPF_CHAN_STAT  0x24

#define NBPF_CHAN_STAT_EN   1

#define NBPF_CHAN_STAT_TACT 4

#define NBPF_CHAN_STAT_ERR  0x10

#define NBPF_CHAN_STAT_END  0x20

#define NBPF_CHAN_STAT_TC   0x40

#define NBPF_CHAN_STAT_DER  0x400

​

/* Channel Control register */

#define NBPF_CHAN_CTRL  0x28

#define NBPF_CHAN_CTRL_SETEN    1

#define NBPF_CHAN_CTRL_CLREN    2

#define NBPF_CHAN_CTRL_STG  4

#define NBPF_CHAN_CTRL_SWRST    8

#define NBPF_CHAN_CTRL_CLRRQ    0x10

#define NBPF_CHAN_CTRL_CLREND   0x20

#define NBPF_CHAN_CTRL_CLRTC    0x40

#define NBPF_CHAN_CTRL_SETSUS   0x100

#define NBPF_CHAN_CTRL_CLRSUS   0x200

​

/* Channel Configuration register */

#define NBPF_CHAN_CFG   0x2c

#define NBPF_CHAN_CFG_SEL   7       /* terminal SELect: 0..7 */

#define NBPF_CHAN_CFG_REQD  8       /* REQuest Direction: DMAREQ is 0: input, 1: output */

#define NBPF_CHAN_CFG_LOEN  0x10        /* LOw ENable: low DMA request line is: 0: inactive, 1: active */

#define NBPF_CHAN_CFG_HIEN  0x20        /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */

#define NBPF_CHAN_CFG_LVL   0x40        /* LeVeL: DMA request line is sensed as 0: edge, 1: level */

#define NBPF_CHAN_CFG_AM    0x700       /* ACK Mode: 0: Pulse mode, 1: Level mode, b'1x: Bus Cycle */

#define NBPF_CHAN_CFG_SDS   0xf000      /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */

#define NBPF_CHAN_CFG_DDS   0xf0000     /* Destination Data Size: as above */