linux-imx

/*

 * Copyright (C) 2017 Spreadtrum Communications Inc.

 *

 * SPDX-License-Identifier: GPL-2.0

 */

​

#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/dma/sprd-dma.h>

#include <linux/errno.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_dma.h>

#include <linux/of_device.h>

#include <linux/pm_runtime.h>

#include <linux/slab.h>

​

#include "virt-dma.h"

​

#define SPRD_DMA_CHN_REG_OFFSET     0x1000

#define SPRD_DMA_CHN_REG_LENGTH     0x40

#define SPRD_DMA_MEMCPY_MIN_SIZE    64

​

/* DMA global registers definition */

#define SPRD_DMA_GLB_PAUSE      0x0

#define SPRD_DMA_GLB_FRAG_WAIT      0x4

#define SPRD_DMA_GLB_REQ_PEND0_EN   0x8

#define SPRD_DMA_GLB_REQ_PEND1_EN   0xc

#define SPRD_DMA_GLB_INT_RAW_STS    0x10

#define SPRD_DMA_GLB_INT_MSK_STS    0x14

#define SPRD_DMA_GLB_REQ_STS        0x18

#define SPRD_DMA_GLB_CHN_EN_STS     0x1c

#define SPRD_DMA_GLB_DEBUG_STS      0x20

#define SPRD_DMA_GLB_ARB_SEL_STS    0x24

#define SPRD_DMA_GLB_2STAGE_GRP1    0x28

#define SPRD_DMA_GLB_2STAGE_GRP2    0x2c

#define SPRD_DMA_GLB_REQ_UID(uid)   (0x4 * ((uid) - 1))

#define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000

​

/* DMA channel registers definition */

#define SPRD_DMA_CHN_PAUSE      0x0

#define SPRD_DMA_CHN_REQ        0x4

#define SPRD_DMA_CHN_CFG        0x8

#define SPRD_DMA_CHN_INTC       0xc

#define SPRD_DMA_CHN_SRC_ADDR       0x10

#define SPRD_DMA_CHN_DES_ADDR       0x14

#define SPRD_DMA_CHN_FRG_LEN        0x18

#define SPRD_DMA_CHN_BLK_LEN        0x1c

#define SPRD_DMA_CHN_TRSC_LEN       0x20

#define SPRD_DMA_CHN_TRSF_STEP      0x24

#define SPRD_DMA_CHN_WARP_PTR       0x28

#define SPRD_DMA_CHN_WARP_TO        0x2c

#define SPRD_DMA_CHN_LLIST_PTR      0x30

#define SPRD_DMA_CHN_FRAG_STEP      0x34

#define SPRD_DMA_CHN_SRC_BLK_STEP   0x38

#define SPRD_DMA_CHN_DES_BLK_STEP   0x3c

​

/* SPRD_DMA_GLB_2STAGE_GRP register definition */

#define SPRD_DMA_GLB_2STAGE_EN      BIT(24)

#define SPRD_DMA_GLB_CHN_INT_MASK   GENMASK(23, 20)

#define SPRD_DMA_GLB_LIST_DONE_TRG  BIT(19)

#define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18)

#define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17)

#define SPRD_DMA_GLB_FRAG_DONE_TRG  BIT(16)

#define SPRD_DMA_GLB_TRG_OFFSET     16

#define SPRD_DMA_GLB_DEST_CHN_MASK  GENMASK(13, 8)

#define SPRD_DMA_GLB_DEST_CHN_OFFSET    8

#define SPRD_DMA_GLB_SRC_CHN_MASK   GENMASK(5, 0)

​

/* SPRD_DMA_CHN_INTC register definition */

#define SPRD_DMA_INT_MASK       GENMASK(4, 0)

#define SPRD_DMA_INT_CLR_OFFSET     24

#define SPRD_DMA_FRAG_INT_EN        BIT(0)

#define SPRD_DMA_BLK_INT_EN     BIT(1)

#define SPRD_DMA_TRANS_INT_EN       BIT(2)

#define SPRD_DMA_LIST_INT_EN        BIT(3)

#define SPRD_DMA_CFG_ERR_INT_EN     BIT(4)

​

/* SPRD_DMA_CHN_CFG register definition */

#define SPRD_DMA_CHN_EN         BIT(0)

#define SPRD_DMA_LINKLIST_EN        BIT(4)

#define SPRD_DMA_WAIT_BDONE_OFFSET  24

#define SPRD_DMA_DONOT_WAIT_BDONE   1

​

/* SPRD_DMA_CHN_REQ register definition */

#define SPRD_DMA_REQ_EN         BIT(0)

​

/* SPRD_DMA_CHN_PAUSE register definition */