linux-imx

/*

 * Driver for STM32 DMA controller

 *

 * Inspired by dma-jz4740.c and tegra20-apb-dma.c

 *

 * Copyright (C) M'boumba Cedric Madianga 2015

 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>

 *         Pierre-Yves Mordret <pierre-yves.mordret@st.com>

 *

 * License terms:  GNU General Public License (GPL), version 2

 */

​

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/dmaengine.h>

#include <linux/dma-mapping.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/jiffies.h>

#include <linux/list.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_dma.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/reset.h>

#include <linux/sched.h>

#include <linux/slab.h>

​

#include "virt-dma.h"

​

#define STM32_DMA_LISR          0x0000 /* DMA Low Int Status Reg */

#define STM32_DMA_HISR          0x0004 /* DMA High Int Status Reg */

#define STM32_DMA_LIFCR         0x0008 /* DMA Low Int Flag Clear Reg */

#define STM32_DMA_HIFCR         0x000c /* DMA High Int Flag Clear Reg */

#define STM32_DMA_TCI           BIT(5) /* Transfer Complete Interrupt */

#define STM32_DMA_HTI           BIT(4) /* Half Transfer Interrupt */

#define STM32_DMA_TEI           BIT(3) /* Transfer Error Interrupt */

#define STM32_DMA_DMEI          BIT(2) /* Direct Mode Error Interrupt */

#define STM32_DMA_FEI           BIT(0) /* FIFO Error Interrupt */

#define STM32_DMA_MASKI         (STM32_DMA_TCI \

                     | STM32_DMA_TEI \

                     | STM32_DMA_DMEI \

                     | STM32_DMA_FEI)

​

/* DMA Stream x Configuration Register */

#define STM32_DMA_SCR(x)        (0x0010 + 0x18 * (x)) /* x = 0..7 */

#define STM32_DMA_SCR_REQ(n)        ((n & 0x7) << 25)

#define STM32_DMA_SCR_MBURST_MASK   GENMASK(24, 23)

#define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)

#define STM32_DMA_SCR_PBURST_MASK   GENMASK(22, 21)

#define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)

#define STM32_DMA_SCR_PL_MASK       GENMASK(17, 16)

#define STM32_DMA_SCR_PL(n)     ((n & 0x3) << 16)

#define STM32_DMA_SCR_MSIZE_MASK    GENMASK(14, 13)

#define STM32_DMA_SCR_MSIZE(n)      ((n & 0x3) << 13)

#define STM32_DMA_SCR_PSIZE_MASK    GENMASK(12, 11)

#define STM32_DMA_SCR_PSIZE(n)      ((n & 0x3) << 11)

#define STM32_DMA_SCR_PSIZE_GET(n)  ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)

#define STM32_DMA_SCR_DIR_MASK      GENMASK(7, 6)

#define STM32_DMA_SCR_DIR(n)        ((n & 0x3) << 6)

#define STM32_DMA_SCR_CT        BIT(19) /* Target in double buffer */

#define STM32_DMA_SCR_DBM       BIT(18) /* Double Buffer Mode */

#define STM32_DMA_SCR_PINCOS        BIT(15) /* Peripheral inc offset size */

#define STM32_DMA_SCR_MINC      BIT(10) /* Memory increment mode */

#define STM32_DMA_SCR_PINC      BIT(9) /* Peripheral increment mode */

#define STM32_DMA_SCR_CIRC      BIT(8) /* Circular mode */

#define STM32_DMA_SCR_PFCTRL        BIT(5) /* Peripheral Flow Controller */

#define STM32_DMA_SCR_TCIE      BIT(4) /* Transfer Complete Int Enable

                        */

#define STM32_DMA_SCR_TEIE      BIT(2) /* Transfer Error Int Enable */

#define STM32_DMA_SCR_DMEIE     BIT(1) /* Direct Mode Err Int Enable */

#define STM32_DMA_SCR_EN        BIT(0) /* Stream Enable */

#define STM32_DMA_SCR_CFG_MASK      (STM32_DMA_SCR_PINC \

                    | STM32_DMA_SCR_MINC \

                    | STM32_DMA_SCR_PINCOS \

                    | STM32_DMA_SCR_PL_MASK)

#define STM32_DMA_SCR_IRQ_MASK      (STM32_DMA_SCR_TCIE \

                    | STM32_DMA_SCR_TEIE \

                    | STM32_DMA_SCR_DMEIE)

​

/* DMA Stream x number of data register */

#define STM32_DMA_SNDTR(x)      (0x0014 + 0x18 * (x))

​

/* DMA stream peripheral address register */

#define STM32_DMA_SPAR(x)       (0x0018 + 0x18 * (x))

​

/* DMA stream x memory 0 address register */

#define STM32_DMA_SM0AR(x)      (0x001c + 0x18 * (x))

​

/* DMA stream x memory 1 address register */