linux-imx

/*

 * Copyright (C) 2014 Emilio López

 * Emilio López <emilio@elopez.com.ar>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

​

#include <linux/bitmap.h>

#include <linux/bitops.h>

#include <linux/clk.h>

#include <linux/dmaengine.h>

#include <linux/dmapool.h>

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/of_dma.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

#include "virt-dma.h"

​

/** Common macros to normal and dedicated DMA registers **/

​

#define SUN4I_DMA_CFG_LOADING           BIT(31)

#define SUN4I_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 25)

#define SUN4I_DMA_CFG_DST_BURST_LENGTH(len) ((len) << 23)

#define SUN4I_DMA_CFG_DST_ADDR_MODE(mode)   ((mode) << 21)

#define SUN4I_DMA_CFG_DST_DRQ_TYPE(type)    ((type) << 16)

#define SUN4I_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 9)

#define SUN4I_DMA_CFG_SRC_BURST_LENGTH(len) ((len) << 7)

#define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode)   ((mode) << 5)

#define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type)    (type)

​

/** Normal DMA register values **/

​

/* Normal DMA source/destination data request type values */

#define SUN4I_NDMA_DRQ_TYPE_SDRAM       0x16

#define SUN4I_NDMA_DRQ_TYPE_LIMIT       (0x1F + 1)

​

/** Normal DMA register layout **/

​

/* Dedicated DMA source/destination address mode values */

#define SUN4I_NDMA_ADDR_MODE_LINEAR     0

#define SUN4I_NDMA_ADDR_MODE_IO         1

​

/* Normal DMA configuration register layout */

#define SUN4I_NDMA_CFG_CONT_MODE        BIT(30)

#define SUN4I_NDMA_CFG_WAIT_STATE(n)        ((n) << 27)

#define SUN4I_NDMA_CFG_DST_NON_SECURE       BIT(22)

#define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN   BIT(15)

#define SUN4I_NDMA_CFG_SRC_NON_SECURE       BIT(6)

​

/** Dedicated DMA register values **/

​

/* Dedicated DMA source/destination address mode values */

#define SUN4I_DDMA_ADDR_MODE_LINEAR     0

#define SUN4I_DDMA_ADDR_MODE_IO         1

#define SUN4I_DDMA_ADDR_MODE_HORIZONTAL_PAGE    2

#define SUN4I_DDMA_ADDR_MODE_VERTICAL_PAGE  3

​

/* Dedicated DMA source/destination data request type values */

#define SUN4I_DDMA_DRQ_TYPE_SDRAM       0x1

#define SUN4I_DDMA_DRQ_TYPE_LIMIT       (0x1F + 1)

​

/** Dedicated DMA register layout **/

​

/* Dedicated DMA configuration register layout */

#define SUN4I_DDMA_CFG_BUSY         BIT(30)

#define SUN4I_DDMA_CFG_CONT_MODE        BIT(29)

#define SUN4I_DDMA_CFG_DST_NON_SECURE       BIT(28)

#define SUN4I_DDMA_CFG_BYTE_COUNT_MODE_REMAIN   BIT(15)

#define SUN4I_DDMA_CFG_SRC_NON_SECURE       BIT(12)

​

/* Dedicated DMA parameter register layout */

#define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n)    (((n) - 1) << 24)

#define SUN4I_DDMA_PARA_DST_WAIT_CYCLES(n)  (((n) - 1) << 16)

#define SUN4I_DDMA_PARA_SRC_DATA_BLK_SIZE(n)    (((n) - 1) << 8)

#define SUN4I_DDMA_PARA_SRC_WAIT_CYCLES(n)  (((n) - 1) << 0)

​

/** DMA register offsets **/

​

/* General register offsets */

#define SUN4I_DMA_IRQ_ENABLE_REG        0x0

#define SUN4I_DMA_IRQ_PENDING_STATUS_REG    0x4

​

/* Normal DMA register offsets */

#define SUN4I_NDMA_CHANNEL_REG_BASE(n)      (0x100 + (n) * 0x20)

#define SUN4I_NDMA_CFG_REG          0x0

#define SUN4I_NDMA_SRC_ADDR_REG         0x4