linux-imx

// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2018, 2019 Cisco Systems

 */

​

#include <linux/edac.h>

#include <linux/module.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/stop_machine.h>

#include <linux/io.h>

#include <linux/of_address.h>

#include <linux/regmap.h>

#include "edac_module.h"

​

​

#define DRV_NAME "aspeed-edac"

​

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#define ASPEED_MCR_PROT        0x00 /* protection key register */

#define ASPEED_MCR_CONF        0x04 /* configuration register */

#define ASPEED_MCR_INTR_CTRL   0x50 /* interrupt control/status register */

#define ASPEED_MCR_ADDR_UNREC  0x58 /* address of first un-recoverable error */

#define ASPEED_MCR_ADDR_REC    0x5c /* address of last recoverable error */

#define ASPEED_MCR_LAST        ASPEED_MCR_ADDR_REC

​

​

#define ASPEED_MCR_PROT_PASSWD              0xfc600309

#define ASPEED_MCR_CONF_DRAM_TYPE               BIT(4)

#define ASPEED_MCR_CONF_ECC                     BIT(7)

#define ASPEED_MCR_INTR_CTRL_CLEAR             BIT(31)

#define ASPEED_MCR_INTR_CTRL_CNT_REC   GENMASK(23, 16)

#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)

#define ASPEED_MCR_INTR_CTRL_ENABLE  (BIT(0) | BIT(1))

​

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static struct regmap *aspeed_regmap;

​

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static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)

{

    void __iomem *regs = (void __iomem *)context;

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    /* enable write to MCR register set */

    writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);

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    writel(val, regs + reg);

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    /* disable write to MCR register set */

    writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);

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    return 0;

}

​

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static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)

{

    void __iomem *regs = (void __iomem *)context;

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    *val = readl(regs + reg);

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    return 0;

}

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static bool regmap_is_volatile(struct device *dev, unsigned int reg)

{

    switch (reg) {

    case ASPEED_MCR_PROT:

    case ASPEED_MCR_INTR_CTRL:

    case ASPEED_MCR_ADDR_UNREC:

    case ASPEED_MCR_ADDR_REC:

        return true;

    default:

        return false;

    }

}

​

​

static const struct regmap_config aspeed_regmap_config = {

    .reg_bits = 32,

    .val_bits = 32,

    .reg_stride = 4,

    .max_register = ASPEED_MCR_LAST,

    .reg_write = regmap_reg_write,

    .reg_read = regmap_reg_read,

    .volatile_reg = regmap_is_volatile,

    .fast_io = true,

};

​

​

static void count_rec(struct mem_ctl_info *mci, u8 rec_cnt, u32 rec_addr)