linux-imx

/*

 * Radisys 82600 Embedded chipset Memory Controller kernel module

 * (C) 2005 EADS Astrium

 * This file may be distributed under the terms of the

 * GNU General Public License.

 *

 * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne

 * Harbaugh, Dan Hollis <goemon at anime dot net> and others.

 *

 * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $

 *

 * Written with reference to 82600 High Integration Dual PCI System

 * Controller Data Book:

 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf

 * references to this document given in []

 */

​

#include <linux/module.h>

#include <linux/init.h>

#include <linux/pci.h>

#include <linux/pci_ids.h>

#include <linux/edac.h>

#include "edac_module.h"

​

#define EDAC_MOD_STR    "r82600_edac"

​

#define r82600_printk(level, fmt, arg...) \

    edac_printk(level, "r82600", fmt, ##arg)

​

#define r82600_mc_printk(mci, level, fmt, arg...) \

    edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)

​

/* Radisys say "The 82600 integrates a main memory SDRAM controller that

 * supports up to four banks of memory. The four banks can support a mix of

 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,

 * each of which can be any size from 16MB to 512MB. Both registered (control

 * signals buffered) and unbuffered DIMM types are supported. Mixing of

 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs

 * is not allowed. The 82600 SDRAM interface operates at the same frequency as

 * the CPU bus, 66MHz, 100MHz or 133MHz."

 */

​

#define R82600_NR_CSROWS 4

#define R82600_NR_CHANS  1

#define R82600_NR_DIMMS  4

​

#define R82600_BRIDGE_ID  0x8200

​

/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */

#define R82600_DRAMC    0x57    /* Various SDRAM related control bits

                 * all bits are R/W

                 *

                 * 7    SDRAM ISA Hole Enable

                 * 6    Flash Page Mode Enable

                 * 5    ECC Enable: 1=ECC 0=noECC

                 * 4    DRAM DIMM Type: 1=

                 * 3    BIOS Alias Disable

                 * 2    SDRAM BIOS Flash Write Enable

                 * 1:0  SDRAM Refresh Rate: 00=Disabled

                 *          01=7.8usec (256Mbit SDRAMs)

                 *          10=15.6us 11=125usec

                 */

​