linux-imx

/*

 * Synopsys DDR ECC Driver

 * This driver is based on ppc4xx_edac.c drivers

 *

 * Copyright (C) 2012 - 2014 Xilinx, Inc.

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details

 */

​

#include <linux/edac.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/interrupt.h>

#include <linux/of.h>

#include <linux/of_device.h>

​

#include "edac_module.h"

​

/* Number of cs_rows needed per memory controller */

#define SYNPS_EDAC_NR_CSROWS        1

​

/* Number of channels per memory controller */

#define SYNPS_EDAC_NR_CHANS     1

​

/* Granularity of reported error in bytes */

#define SYNPS_EDAC_ERR_GRAIN        1

​

#define SYNPS_EDAC_MSG_SIZE     256

​

#define SYNPS_EDAC_MOD_STRING       "synps_edac"

#define SYNPS_EDAC_MOD_VER      "1"

​

/* Synopsys DDR memory controller registers that are relevant to ECC */

#define CTRL_OFST           0x0

#define T_ZQ_OFST           0xA4

​

/* ECC control register */

#define ECC_CTRL_OFST           0xC4

/* ECC log register */

#define CE_LOG_OFST         0xC8

/* ECC address register */

#define CE_ADDR_OFST            0xCC

/* ECC data[31:0] register */

#define CE_DATA_31_0_OFST       0xD0

​

/* Uncorrectable error info registers */

#define UE_LOG_OFST         0xDC

#define UE_ADDR_OFST            0xE0

#define UE_DATA_31_0_OFST       0xE4

​

#define STAT_OFST           0xF0

#define SCRUB_OFST          0xF4

​

/* Control register bit field definitions */

#define CTRL_BW_MASK            0xC

#define CTRL_BW_SHIFT           2

​

#define DDRCTL_WDTH_16          1

#define DDRCTL_WDTH_32          0

​

/* ZQ register bit field definitions */

#define T_ZQ_DDRMODE_MASK       0x2

​

/* ECC control register bit field definitions */

#define ECC_CTRL_CLR_CE_ERR     0x2

#define ECC_CTRL_CLR_UE_ERR     0x1

​

/* ECC correctable/uncorrectable error log register definitions */

#define LOG_VALID           0x1

#define CE_LOG_BITPOS_MASK      0xFE

#define CE_LOG_BITPOS_SHIFT     1

​

/* ECC correctable/uncorrectable error address register definitions */

#define ADDR_COL_MASK           0xFFF

#define ADDR_ROW_MASK           0xFFFF000

#define ADDR_ROW_SHIFT          12

#define ADDR_BANK_MASK          0x70000000

#define ADDR_BANK_SHIFT         28

​

/* ECC statistic register definitions */