linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/

 *

 * Texas Instruments DDR3 ECC error correction and detection driver

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

​

#include <linux/init.h>

#include <linux/edac.h>

#include <linux/io.h>

#include <linux/interrupt.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/module.h>

​

#include "edac_module.h"

​

/* EMIF controller registers */

#define EMIF_SDRAM_CONFIG       0x008

#define EMIF_IRQ_STATUS         0x0ac

#define EMIF_IRQ_ENABLE_SET     0x0b4

#define EMIF_ECC_CTRL           0x110

#define EMIF_1B_ECC_ERR_CNT     0x130

#define EMIF_1B_ECC_ERR_THRSH       0x134

#define EMIF_1B_ECC_ERR_ADDR_LOG    0x13c

#define EMIF_2B_ECC_ERR_ADDR_LOG    0x140

​

/* Bit definitions for EMIF_SDRAM_CONFIG */

#define SDRAM_TYPE_SHIFT        29

#define SDRAM_TYPE_MASK         GENMASK(31, 29)

#define SDRAM_TYPE_DDR3         (3 << SDRAM_TYPE_SHIFT)

#define SDRAM_TYPE_DDR2         (2 << SDRAM_TYPE_SHIFT)

#define SDRAM_NARROW_MODE_MASK      GENMASK(15, 14)

#define SDRAM_K2_NARROW_MODE_SHIFT  12

#define SDRAM_K2_NARROW_MODE_MASK   GENMASK(13, 12)

#define SDRAM_ROWSIZE_SHIFT     7

#define SDRAM_ROWSIZE_MASK      GENMASK(9, 7)

#define SDRAM_IBANK_SHIFT       4

#define SDRAM_IBANK_MASK        GENMASK(6, 4)

#define SDRAM_K2_IBANK_SHIFT        5

#define SDRAM_K2_IBANK_MASK     GENMASK(6, 5)

#define SDRAM_K2_EBANK_SHIFT        3

#define SDRAM_K2_EBANK_MASK     BIT(SDRAM_K2_EBANK_SHIFT)

#define SDRAM_PAGESIZE_SHIFT        0

#define SDRAM_PAGESIZE_MASK     GENMASK(2, 0)

#define SDRAM_K2_PAGESIZE_SHIFT     0

#define SDRAM_K2_PAGESIZE_MASK      GENMASK(1, 0)

​

#define EMIF_1B_ECC_ERR_THRSH_SHIFT 24

​

/* IRQ bit definitions */