linux-imx

/*

 * Intel X38 Memory Controller kernel module

 * Copyright (C) 2008 Cluster Computing, Inc.

 *

 * This file may be distributed under the terms of the

 * GNU General Public License.

 *

 * This file is based on i3200_edac.c

 *

 */

​

#include <linux/module.h>

#include <linux/init.h>

#include <linux/pci.h>

#include <linux/pci_ids.h>

#include <linux/edac.h>

​

#include <linux/io-64-nonatomic-lo-hi.h>

#include "edac_module.h"

​

#define EDAC_MOD_STR        "x38_edac"

​

#define PCI_DEVICE_ID_INTEL_X38_HB  0x29e0

​

#define X38_RANKS       8

#define X38_RANKS_PER_CHANNEL   4

#define X38_CHANNELS        2

​

/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */

​

#define X38_MCHBAR_LOW  0x48    /* MCH Memory Mapped Register BAR */

#define X38_MCHBAR_HIGH 0x4c

#define X38_MCHBAR_MASK 0xfffffc000ULL  /* bits 35:14 */

#define X38_MMR_WINDOW_SIZE 16384

​

#define X38_TOM 0xa0    /* Top of Memory (16b)

                 *

                 * 15:10 reserved

                 *  9:0  total populated physical memory

                 */

#define X38_TOM_MASK    0x3ff   /* bits 9:0 */

#define X38_TOM_SHIFT 26    /* 64MiB grain */

​

#define X38_ERRSTS  0xc8    /* Error Status Register (16b)

                 *

                 * 15    reserved

                 * 14    Isochronous TBWRR Run Behind FIFO Full

                 *       (ITCV)

                 * 13    Isochronous TBWRR Run Behind FIFO Put

                 *       (ITSTV)

                 * 12    reserved

                 * 11    MCH Thermal Sensor Event

                 *       for SMI/SCI/SERR (GTSE)

                 * 10    reserved

                 *  9    LOCK to non-DRAM Memory Flag (LCKF)

                 *  8    reserved

                 *  7    DRAM Throttle Flag (DTF)

                 *  6:2  reserved

                 *  1    Multi-bit DRAM ECC Error Flag (DMERR)

                 *  0    Single-bit DRAM ECC Error Flag (DSERR)

                 */

#define X38_ERRSTS_UE       0x0002

#define X38_ERRSTS_CE       0x0001

#define X38_ERRSTS_BITS (X38_ERRSTS_UE | X38_ERRSTS_CE)

​

​

/* Intel  MMIO register space - device 0 function 0 - MMR space */

​

#define X38_C0DRB   0x200   /* Channel 0 DRAM Rank Boundary (16b x 4)

                 *

                 * 15:10 reserved

                 *  9:0  Channel 0 DRAM Rank Boundary Address

                 */

#define X38_C1DRB   0x600   /* Channel 1 DRAM Rank Boundary (16b x 4) */

#define X38_DRB_MASK    0x3ff   /* bits 9:0 */

#define X38_DRB_SHIFT 26    /* 64MiB grain */

​

#define X38_C0ECCERRLOG 0x280   /* Channel 0 ECC Error Log (64b)

                 *

                 * 63:48 Error Column Address (ERRCOL)

                 * 47:32 Error Row Address (ERRROW)

                 * 31:29 Error Bank Address (ERRBANK)

                 * 28:27 Error Rank Address (ERRRANK)

                 * 26:24 reserved

                 * 23:16 Error Syndrome (ERRSYND)

                 * 15: 2 reserved

                 *    1  Multiple Bit Error Status (MERRSTS)

                 *    0  Correctable Error Status (CERRSTS)

                 */

#define X38_C1ECCERRLOG 0x680   /* Channel 1 ECC Error Log (64b) */

#define X38_ECCERRLOG_CE    0x1

#define X38_ECCERRLOG_UE    0x2