linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices

 *

 *  Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.

 */

​

/*

 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM

 * host processor system (HPS).

 *

 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.

 * Reconfiguring these ports requires that no SDRAM transactions occur during

 * reconfiguration.  The code reconfiguring the ports cannot run out of SDRAM

 * nor can the FPGA access the SDRAM during reconfiguration.  This driver does

 * not support reconfiguring the ports.  The ports are configured by code

 * running out of on chip ram before Linux is started and the configuration

 * is passed in a handoff register in the system manager.

 *

 * This driver supports enabling and disabling of the configured ports, which

 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image

 * uses the same port configuration.  Bridges must be disabled before

 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.

 */

​

#include <linux/fpga/fpga-bridge.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of_platform.h>

#include <linux/regmap.h>

​

#define ALT_SDR_CTL_FPGAPORTRST_OFST        0x80

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK    0x00003fff

#define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT    0

#define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT    4

#define ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT  8

​

/*

 * From the Cyclone V HPS Memory Map document:

 *   These registers are used to store handoff information between the

 *   preloader and the OS. These 8 registers can be used to store any

 *   information. The contents of these registers have no impact on

 *   the state of the HPS hardware.

 */

#define SYSMGR_ISWGRP_HANDOFF3          (0x8C)

​

#define F2S_BRIDGE_NAME "fpga2sdram"

​

struct alt_fpga2sdram_data {

    struct device *dev;

    struct regmap *sdrctl;

    int mask;

};

​

static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge)

{

    struct alt_fpga2sdram_data *priv = bridge->priv;

    int value;

​

    regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value);

​

    return (value & priv->mask) == priv->mask;