linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Driver for Altera Partial Reconfiguration IP Core

 *

 * Copyright (C) 2016-2017 Intel Corporation

 *

 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation

 *  by Alan Tull <atull@opensource.altera.com>

 */

#include <linux/delay.h>

#include <linux/fpga/altera-pr-ip-core.h>

#include <linux/fpga/fpga-mgr.h>

#include <linux/module.h>

​

#define ALT_PR_DATA_OFST        0x00

#define ALT_PR_CSR_OFST         0x04

​

#define ALT_PR_CSR_PR_START     BIT(0)

#define ALT_PR_CSR_STATUS_SFT       2

#define ALT_PR_CSR_STATUS_MSK       (7 << ALT_PR_CSR_STATUS_SFT)

#define ALT_PR_CSR_STATUS_NRESET    (0 << ALT_PR_CSR_STATUS_SFT)

#define ALT_PR_CSR_STATUS_PR_ERR    (1 << ALT_PR_CSR_STATUS_SFT)

#define ALT_PR_CSR_STATUS_CRC_ERR   (2 << ALT_PR_CSR_STATUS_SFT)

#define ALT_PR_CSR_STATUS_BAD_BITS  (3 << ALT_PR_CSR_STATUS_SFT)

#define ALT_PR_CSR_STATUS_PR_IN_PROG    (4 << ALT_PR_CSR_STATUS_SFT)

#define ALT_PR_CSR_STATUS_PR_SUCCESS    (5 << ALT_PR_CSR_STATUS_SFT)

​

struct alt_pr_priv {

    void __iomem *reg_base;

};

​

static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)

{

    struct alt_pr_priv *priv = mgr->priv;

    const char *err = "unknown";

    enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;

    u32 val;

​

    val = readl(priv->reg_base + ALT_PR_CSR_OFST);

​

    val &= ALT_PR_CSR_STATUS_MSK;

​

    switch (val) {

    case ALT_PR_CSR_STATUS_NRESET:

        return FPGA_MGR_STATE_RESET;

​

    case ALT_PR_CSR_STATUS_PR_ERR:

        err = "pr error";

        ret = FPGA_MGR_STATE_WRITE_ERR;

        break;

​

    case ALT_PR_CSR_STATUS_CRC_ERR:

        err = "crc error";

        ret = FPGA_MGR_STATE_WRITE_ERR;

        break;

​

    case ALT_PR_CSR_STATUS_BAD_BITS:

        err = "bad bits";

        ret = FPGA_MGR_STATE_WRITE_ERR;

        break;

​

    case ALT_PR_CSR_STATUS_PR_IN_PROG:

        return FPGA_MGR_STATE_WRITE;

​

    case ALT_PR_CSR_STATUS_PR_SUCCESS:

        return FPGA_MGR_STATE_OPERATING;

​

    default:

        break;

    }

​

    dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",

        val, err, __func__);

    return ret;

}

​

static int alt_pr_fpga_write_init(struct fpga_manager *mgr,

                  struct fpga_image_info *info,

                  const char *buf, size_t count)

{

    struct alt_pr_priv *priv = mgr->priv;

    u32 val;

​

    if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {

        dev_err(&mgr->dev, "%s Partial Reconfiguration flag not set\n",

            __func__);

        return -EINVAL;

    }

​

    val = readl(priv->reg_base + ALT_PR_CSR_OFST);

​

    if (val & ALT_PR_CSR_PR_START) {