linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * FPGA Manager Driver for FPGA Management Engine (FME)

 *

 * Copyright (C) 2017-2018 Intel Corporation, Inc.

 *

 * Authors:

 *   Kang Luwei <luwei.kang@intel.com>

 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>

 *   Wu Hao <hao.wu@intel.com>

 *   Joseph Grecco <joe.grecco@intel.com>

 *   Enno Luebbers <enno.luebbers@intel.com>

 *   Tim Whisonant <tim.whisonant@intel.com>

 *   Ananda Ravuri <ananda.ravuri@intel.com>

 *   Christopher Rauer <christopher.rauer@intel.com>

 *   Henry Mitchel <henry.mitchel@intel.com>

 */

​

#include <linux/bitfield.h>

#include <linux/module.h>

#include <linux/iopoll.h>

#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/fpga/fpga-mgr.h>

​

#include "dfl-fme-pr.h"

​

/* FME Partial Reconfiguration Sub Feature Register Set */

#define FME_PR_DFH      0x0

#define FME_PR_CTRL     0x8

#define FME_PR_STS      0x10

#define FME_PR_DATA     0x18

#define FME_PR_ERR      0x20

#define FME_PR_INTFC_ID_H   0xA8

#define FME_PR_INTFC_ID_L   0xB0

​

/* FME PR Control Register Bitfield */

#define FME_PR_CTRL_PR_RST  BIT_ULL(0)  /* Reset PR engine */

#define FME_PR_CTRL_PR_RSTACK   BIT_ULL(4)  /* Ack for PR engine reset */

#define FME_PR_CTRL_PR_RGN_ID   GENMASK_ULL(9, 7)       /* PR Region ID */

#define FME_PR_CTRL_PR_START    BIT_ULL(12) /* Start to request PR service */

#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */

​

/* FME PR Status Register Bitfield */

/* Number of available entries in HW queue inside the PR engine. */

#define FME_PR_STS_PR_CREDIT    GENMASK_ULL(8, 0)

#define FME_PR_STS_PR_STS   BIT_ULL(16) /* PR operation status */

#define FME_PR_STS_PR_STS_IDLE  0

#define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20)     /* Controller status */

#define FME_PR_STS_PR_HOST_STS  GENMASK_ULL(27, 24)     /* PR host status */

​

/* FME PR Data Register Bitfield */

/* PR data from the raw-binary file. */

#define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)

​

/* FME PR Error Register */

/* PR Operation errors detected. */

#define FME_PR_ERR_OPERATION_ERR    BIT_ULL(0)

/* CRC error detected. */

#define FME_PR_ERR_CRC_ERR      BIT_ULL(1)

/* Incompatible PR bitstream detected. */

#define FME_PR_ERR_INCOMPATIBLE_BS  BIT_ULL(2)

/* PR data push protocol violated. */

#define FME_PR_ERR_PROTOCOL_ERR     BIT_ULL(3)

/* PR data fifo overflow error detected */

#define FME_PR_ERR_FIFO_OVERFLOW    BIT_ULL(4)

​

#define PR_WAIT_TIMEOUT   8000000

#define PR_HOST_STATUS_IDLE 0

​

struct fme_mgr_priv {

    void __iomem *ioaddr;

    u64 pr_error;

};

​

static u64 pr_error_to_mgr_status(u64 err)

{

    u64 status = 0;

​

    if (err & FME_PR_ERR_OPERATION_ERR)

        status |= FPGA_MGR_STATUS_OPERATION_ERR;

    if (err & FME_PR_ERR_CRC_ERR)

        status |= FPGA_MGR_STATUS_CRC_ERR;

    if (err & FME_PR_ERR_INCOMPATIBLE_BS)

        status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;

    if (err & FME_PR_ERR_PROTOCOL_ERR)

        status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;

    if (err & FME_PR_ERR_FIFO_OVERFLOW)

        status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;

​

    return status;

}

​