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committed fea82b7f667 * struct dfl_feature_info - sub feature info collected during feature dev build// SPDX-License-Identifier: GPL-2.0/* * Driver for FPGA Device Feature List (DFL) Support * * Copyright (C) 2017-2018 Intel Corporation, Inc. * * Authors: * Kang Luwei <luwei.kang@intel.com> * Zhang Yi <yi.z.zhang@intel.com> * Wu Hao <hao.wu@intel.com> * Xiao Guangrong <guangrong.xiao@linux.intel.com> */static DEFINE_MUTEX(dfl_id_mutex);/* * when adding a new feature dev support in DFL framework, it's required to * add a new item in enum dfl_id_type and provide related information in below * dfl_devs table which is indexed by dfl_id_type, e.g. name string used for * platform device creation (define name strings in dfl.h, as they could be * reused by platform device drivers). * * if the new feature dev needs chardev support, then it's required to add * a new item in dfl_chardevs table and configure dfl_devs[i].devt_type as * index to dfl_chardevs table. If no chardev support just set devt_type * as one invalid index (DFL_FPGA_DEVT_MAX). */enum dfl_id_type { FME_ID, /* fme id allocation and mapping */ PORT_ID, /* port id allocation and mapping */ DFL_ID_MAX,};enum dfl_fpga_devt_type { DFL_FPGA_DEVT_FME, DFL_FPGA_DEVT_PORT, DFL_FPGA_DEVT_MAX,};/** * dfl_dev_info - dfl feature device information. * @name: name string of the feature platform device. * @dfh_id: id value in Device Feature Header (DFH) register by DFL spec. * @id: idr id of the feature dev. * @devt_type: index to dfl_chrdevs[]. */struct dfl_dev_info { const char *name; u32 dfh_id; struct idr id; enum dfl_fpga_devt_type devt_type;};/* it is indexed by dfl_id_type */static struct dfl_dev_info dfl_devs[] = { {.name = DFL_FPGA_FEATURE_DEV_FME, .dfh_id = DFH_ID_FIU_FME, .devt_type = DFL_FPGA_DEVT_FME}, {.name = DFL_FPGA_FEATURE_DEV_PORT, .dfh_id = DFH_ID_FIU_PORT, .devt_type = DFL_FPGA_DEVT_PORT},};