linux-imx

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Driver Header File for FPGA Device Feature List (DFL) Support

 *

 * Copyright (C) 2017-2018 Intel Corporation, Inc.

 *

 * Authors:

 *   Kang Luwei <luwei.kang@intel.com>

 *   Zhang Yi <yi.z.zhang@intel.com>

 *   Wu Hao <hao.wu@intel.com>

 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>

 */

​

#ifndef __FPGA_DFL_H

#define __FPGA_DFL_H

​

#include <linux/bitfield.h>

#include <linux/cdev.h>

#include <linux/delay.h>

#include <linux/fs.h>

#include <linux/iopoll.h>

#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/uuid.h>

#include <linux/fpga/fpga-region.h>

​

/* maximum supported number of ports */

#define MAX_DFL_FPGA_PORT_NUM 4

/* plus one for fme device */

#define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)

​

/* Reserved 0x0 for Header Group Register and 0xff for AFU */

#define FEATURE_ID_FIU_HEADER       0x0

#define FEATURE_ID_AFU          0xff

​

#define FME_FEATURE_ID_HEADER       FEATURE_ID_FIU_HEADER

#define FME_FEATURE_ID_THERMAL_MGMT 0x1

#define FME_FEATURE_ID_POWER_MGMT   0x2

#define FME_FEATURE_ID_GLOBAL_IPERF 0x3

#define FME_FEATURE_ID_GLOBAL_ERR   0x4

#define FME_FEATURE_ID_PR_MGMT      0x5

#define FME_FEATURE_ID_HSSI     0x6

#define FME_FEATURE_ID_GLOBAL_DPERF 0x7

​

#define PORT_FEATURE_ID_HEADER      FEATURE_ID_FIU_HEADER

#define PORT_FEATURE_ID_AFU     FEATURE_ID_AFU

#define PORT_FEATURE_ID_ERROR       0x10

#define PORT_FEATURE_ID_UMSG        0x11

#define PORT_FEATURE_ID_UINT        0x12

#define PORT_FEATURE_ID_STP     0x13

​

/*

 * Device Feature Header Register Set

 *

 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.

 * For AFUs, they have DFH + GUID as common header registers.

 * For private features, they only have DFH register as common header.

 */

#define DFH         0x0

#define GUID_L          0x8

#define GUID_H          0x10

#define NEXT_AFU        0x18

​

#define DFH_SIZE        0x8

​

/* Device Feature Header Register Bitfield */

#define DFH_ID          GENMASK_ULL(11, 0)  /* Feature ID */

#define DFH_ID_FIU_FME      0

#define DFH_ID_FIU_PORT     1

#define DFH_REVISION        GENMASK_ULL(15, 12) /* Feature revision */

#define DFH_NEXT_HDR_OFST   GENMASK_ULL(39, 16) /* Offset to next DFH */

#define DFH_EOL         BIT_ULL(40)     /* End of list */

#define DFH_TYPE        GENMASK_ULL(63, 60) /* Feature type */

#define DFH_TYPE_AFU        1

#define DFH_TYPE_PRIVATE    3

#define DFH_TYPE_FIU        4

​

/* Next AFU Register Bitfield */

#define NEXT_AFU_NEXT_DFH_OFST  GENMASK_ULL(23, 0)  /* Offset to next AFU */

​

/* FME Header Register Set */

#define FME_HDR_DFH     DFH

#define FME_HDR_GUID_L      GUID_L

#define FME_HDR_GUID_H      GUID_H

#define FME_HDR_NEXT_AFU    NEXT_AFU

#define FME_HDR_CAP     0x30

#define FME_HDR_PORT_OFST(n)    (0x38 + ((n) * 0x8))

#define FME_HDR_BITSTREAM_ID    0x60

#define FME_HDR_BITSTREAM_MD    0x68

​

/* FME Fab Capability Register Bitfield */