linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * FPGA Manager Driver for Altera SOCFPGA

 *

 *  Copyright (C) 2013-2015 Altera Corporation

 */

#include <linux/completion.h>

#include <linux/delay.h>

#include <linux/fpga/fpga-mgr.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/pm.h>

​

/* Register offsets */

#define SOCFPGA_FPGMGR_STAT_OFST                0x0

#define SOCFPGA_FPGMGR_CTL_OFST                 0x4

#define SOCFPGA_FPGMGR_DCLKCNT_OFST             0x8

#define SOCFPGA_FPGMGR_DCLKSTAT_OFST                0xc

#define SOCFPGA_FPGMGR_GPIO_INTEN_OFST              0x830

#define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST             0x834

#define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST          0x838

#define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST            0x83c

#define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST            0x840

#define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST            0x844

#define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST          0x84c

#define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST          0x850

​

/* Register bit defines */

/* SOCFPGA_FPGMGR_STAT register mode field values */

#define SOCFPGA_FPGMGR_STAT_POWER_UP                0x0 /*ramping*/

#define SOCFPGA_FPGMGR_STAT_RESET               0x1

#define SOCFPGA_FPGMGR_STAT_CFG                 0x2

#define SOCFPGA_FPGMGR_STAT_INIT                0x3

#define SOCFPGA_FPGMGR_STAT_USER_MODE               0x4

#define SOCFPGA_FPGMGR_STAT_UNKNOWN             0x5

#define SOCFPGA_FPGMGR_STAT_STATE_MASK              0x7

/* This is a flag value that doesn't really happen in this register field */

#define SOCFPGA_FPGMGR_STAT_POWER_OFF               0x0

​

#define MSEL_PP16_FAST_NOAES_NODC               0x0

#define MSEL_PP16_FAST_AES_NODC                 0x1

#define MSEL_PP16_FAST_AESOPT_DC                0x2

#define MSEL_PP16_SLOW_NOAES_NODC               0x4

#define MSEL_PP16_SLOW_AES_NODC                 0x5

#define MSEL_PP16_SLOW_AESOPT_DC                0x6

#define MSEL_PP32_FAST_NOAES_NODC               0x8

#define MSEL_PP32_FAST_AES_NODC                 0x9

#define MSEL_PP32_FAST_AESOPT_DC                0xa

#define MSEL_PP32_SLOW_NOAES_NODC               0xc

#define MSEL_PP32_SLOW_AES_NODC                 0xd

#define MSEL_PP32_SLOW_AESOPT_DC                0xe

#define SOCFPGA_FPGMGR_STAT_MSEL_MASK               0x000000f8

#define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT              3

​

/* SOCFPGA_FPGMGR_CTL register */

#define SOCFPGA_FPGMGR_CTL_EN                   0x00000001

#define SOCFPGA_FPGMGR_CTL_NCE                  0x00000002

#define SOCFPGA_FPGMGR_CTL_NCFGPULL             0x00000004

​

#define CDRATIO_X1                      0x00000000