Source
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/*
* Copyright (c) 2017, National Instruments Corp.
* Copyright (c) 2017, Xilix Inc
*
* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
* Decoupler IP Core.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
struct xlnx_pr_decoupler_data {
void __iomem *io_base;
struct clk *clk;
};
static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
u32 offset, u32 val)
{
writel(val, d->io_base + offset);
}
static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
u32 offset)
{
return readl(d->io_base + offset);
}
static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
{
int err;
struct xlnx_pr_decoupler_data *priv = bridge->priv;
err = clk_enable(priv->clk);
if (err)
return err;
if (enable)
xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
else
xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
clk_disable(priv->clk);
return 0;
}
static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
{
const struct xlnx_pr_decoupler_data *priv = bridge->priv;
u32 status;
int err;
err = clk_enable(priv->clk);
if (err)
return err;
status = readl(priv->io_base);
clk_disable(priv->clk);
return !status;
}
static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
.enable_set = xlnx_pr_decoupler_enable_set,
.enable_show = xlnx_pr_decoupler_enable_show,
};
static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
{ .compatible = "xlnx,pr-decoupler-1.00", },
{ .compatible = "xlnx,pr-decoupler", },
{},
};
MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);