linux-imx

// SPDX-License-Identifier: GPL-2.0+

​

/*

 * GPIO driver for the AMD G series FCH (eg. GX-412TC)

 *

 * Copyright (C) 2018 metux IT consult

 * Author: Enrico Weigelt, metux IT consult <info@metux.net>

 *

 */

​

#include <linux/err.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/gpio/driver.h>

#include <linux/platform_data/gpio/gpio-amd-fch.h>

#include <linux/spinlock.h>

​

#define AMD_FCH_MMIO_BASE       0xFED80000

#define AMD_FCH_GPIO_BANK0_BASE     0x1500

#define AMD_FCH_GPIO_SIZE       0x0300

​

#define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23)

#define AMD_FCH_GPIO_FLAG_WRITE     BIT(22)

#define AMD_FCH_GPIO_FLAG_READ      BIT(16)

​

static struct resource amd_fch_gpio_iores =

    DEFINE_RES_MEM_NAMED(

        AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE,

        AMD_FCH_GPIO_SIZE,

        "amd-fch-gpio-iomem");

​

struct amd_fch_gpio_priv {

    struct platform_device      *pdev;

    struct gpio_chip        gc;

    void __iomem            *base;

    struct amd_fch_gpio_pdata   *pdata;

    spinlock_t          lock;

};

​

static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,

                       unsigned int gpio)

{

    return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);

}

​

static int amd_fch_gpio_direction_input(struct gpio_chip *gc,

                    unsigned int offset)

{

    unsigned long flags;

    struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);

    void __iomem *ptr = amd_fch_gpio_addr(priv, offset);

​

    spin_lock_irqsave(&priv->lock, flags);

    writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);

    spin_unlock_irqrestore(&priv->lock, flags);

​

    return 0;

}

​

static int amd_fch_gpio_direction_output(struct gpio_chip *gc,

                     unsigned int gpio, int value)

{

    unsigned long flags;

    struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);

    void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);

    u32 val;

​

    spin_lock_irqsave(&priv->lock, flags);

​

    val = readl_relaxed(ptr);

    if (value)

        val |= AMD_FCH_GPIO_FLAG_WRITE;

    else

        val &= ~AMD_FCH_GPIO_FLAG_WRITE;

​

    writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);

​

    spin_unlock_irqrestore(&priv->lock, flags);

​

    return 0;

}

​

static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)

{

    int ret;

    unsigned long flags;

    struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);

    void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);

​

    spin_lock_irqsave(&priv->lock, flags);