linux-imx

/*

 * Broadcom Kona GPIO Driver

 *

 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>

 * Copyright (C) 2012-2014 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#include <linux/bitops.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/gpio/driver.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/init.h>

#include <linux/irqdomain.h>

#include <linux/irqchip/chained_irq.h>

​

#define BCM_GPIO_PASSWD             0x00a5a501

#define GPIO_PER_BANK               32

#define GPIO_MAX_BANK_NUM           8

​

#define GPIO_BANK(gpio)             ((gpio) >> 5)

#define GPIO_BIT(gpio)              ((gpio) & (GPIO_PER_BANK - 1))

​

/* There is a GPIO control register for each GPIO */

#define GPIO_CONTROL(gpio)          (0x00000100 + ((gpio) << 2))

​

/* The remaining registers are per GPIO bank */

#define GPIO_OUT_STATUS(bank)           (0x00000000 + ((bank) << 2))

#define GPIO_IN_STATUS(bank)            (0x00000020 + ((bank) << 2))

#define GPIO_OUT_SET(bank)          (0x00000040 + ((bank) << 2))

#define GPIO_OUT_CLEAR(bank)            (0x00000060 + ((bank) << 2))

#define GPIO_INT_STATUS(bank)           (0x00000080 + ((bank) << 2))

#define GPIO_INT_MASK(bank)         (0x000000a0 + ((bank) << 2))

#define GPIO_INT_MSKCLR(bank)           (0x000000c0 + ((bank) << 2))

#define GPIO_PWD_STATUS(bank)           (0x00000500 + ((bank) << 2))

​

#define GPIO_GPPWR_OFFSET           0x00000520

​

#define GPIO_GPCTR0_DBR_SHIFT           5

#define GPIO_GPCTR0_DBR_MASK            0x000001e0

​

#define GPIO_GPCTR0_ITR_SHIFT           3

#define GPIO_GPCTR0_ITR_MASK            0x00000018

#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE     0x00000001

#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE    0x00000002

#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE       0x00000003

​

#define GPIO_GPCTR0_IOTR_MASK           0x00000001

#define GPIO_GPCTR0_IOTR_CMD_0UTPUT     0x00000000

#define GPIO_GPCTR0_IOTR_CMD_INPUT      0x00000001

​

#define GPIO_GPCTR0_DB_ENABLE_MASK      0x00000100

​

#define LOCK_CODE               0xffffffff

#define UNLOCK_CODE             0x00000000

​

struct bcm_kona_gpio {

    void __iomem *reg_base;

    int num_bank;

    raw_spinlock_t lock;

    struct gpio_chip gpio_chip;

    struct irq_domain *irq_domain;

    struct bcm_kona_gpio_bank *banks;

    struct platform_device *pdev;

};

​

struct bcm_kona_gpio_bank {

    int id;

    int irq;

    /* Used in the interrupt handler */

    struct bcm_kona_gpio *kona_gpio;

};

​

static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,

                        int bank_id, u32 lockcode)

{

    writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);

    writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));

}

​

static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,

                    unsigned gpio)