linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * GPIO controller driver for Intel Lynxpoint PCH chipset>

 * Copyright (c) 2012, Intel Corporation.

 *

 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>

 */

​

#include <linux/acpi.h>

#include <linux/bitops.h>

#include <linux/gpio/driver.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/slab.h>

#include <linux/types.h>

​

/* LynxPoint chipset has support for 94 gpio pins */

​

#define LP_NUM_GPIO 94

​

/* Bitmapped register offsets */

#define LP_ACPI_OWNED   0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */

#define LP_GC       0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */

#define LP_INT_STAT 0x80

#define LP_INT_ENABLE   0x90

​

/* Each pin has two 32 bit config registers, starting at 0x100 */

#define LP_CONFIG1  0x100

#define LP_CONFIG2  0x104

​

/* LP_CONFIG1 reg bits */

#define OUT_LVL_BIT BIT(31)

#define IN_LVL_BIT  BIT(30)

#define TRIG_SEL_BIT    BIT(4) /* 0: Edge, 1: Level */

#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */

#define DIR_BIT     BIT(2) /* 0: Output, 1: Input */

#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */

​

/* LP_CONFIG2 reg bits */

#define GPINDIS_BIT BIT(2) /* disable input sensing */

#define GPIWP_BIT   (BIT(0) | BIT(1)) /* weak pull options */

​

struct lp_gpio {

    struct gpio_chip    chip;

    struct platform_device  *pdev;

    spinlock_t      lock;

    unsigned long       reg_base;

};

​

/*

 * Lynxpoint gpios are controlled through both bitmapped registers and

 * per gpio specific registers. The bitmapped registers are in chunks of

 * 3 x 32bit registers to cover all 94 gpios

 *

 * per gpio specific registers consist of two 32bit registers per gpio

 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of

 * 188 config registers.

 *

 * A simplified view of the register layout look like this: