linux-imx

/*

 *  linux/drivers/gpio/gpio-mb86s7x.c

 *

 *  Copyright (C) 2015 Fujitsu Semiconductor Limited

 *  Copyright (C) 2015 Linaro Ltd.

 *

 *  This program is free software: you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License as published by

 *  the Free Software Foundation, version 2 of the License.

 *

 *  This program is distributed in the hope that it will be useful,

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *  GNU General Public License for more details.

 */

​

#include <linux/io.h>

#include <linux/init.h>

#include <linux/clk.h>

#include <linux/module.h>

#include <linux/err.h>

#include <linux/errno.h>

#include <linux/ioport.h>

#include <linux/of_device.h>

#include <linux/gpio/driver.h>

#include <linux/platform_device.h>

#include <linux/spinlock.h>

#include <linux/slab.h>

​

/*

 * Only first 8bits of a register correspond to each pin,

 * so there are 4 registers for 32 pins.

 */

#define PDR(x)  (0x0 + x / 8 * 4)

#define DDR(x)  (0x10 + x / 8 * 4)

#define PFR(x)  (0x20 + x / 8 * 4)

​

#define OFFSET(x)   BIT((x) % 8)

​

struct mb86s70_gpio_chip {

    struct gpio_chip gc;

    void __iomem *base;

    struct clk *clk;

    spinlock_t lock;

};

​

static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)

{

    struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);

    unsigned long flags;

    u32 val;

​

    spin_lock_irqsave(&gchip->lock, flags);

​

    val = readl(gchip->base + PFR(gpio));

    val &= ~OFFSET(gpio);

    writel(val, gchip->base + PFR(gpio));

​

    spin_unlock_irqrestore(&gchip->lock, flags);

​

    return 0;

}

​

static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)

{

    struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);

    unsigned long flags;

    u32 val;

​

    spin_lock_irqsave(&gchip->lock, flags);

​

    val = readl(gchip->base + PFR(gpio));

    val |= OFFSET(gpio);

    writel(val, gchip->base + PFR(gpio));

​

    spin_unlock_irqrestore(&gchip->lock, flags);

}

​

static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)

{

    struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);

    unsigned long flags;

    unsigned char val;

​

    spin_lock_irqsave(&gchip->lock, flags);

​

    val = readl(gchip->base + DDR(gpio));

    val &= ~OFFSET(gpio);

    writel(val, gchip->base + DDR(gpio));

​

    spin_unlock_irqrestore(&gchip->lock, flags);

​