linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2018 Spreadtrum Communications Inc.

 * Copyright (C) 2018 Linaro Ltd.

 */

​

#include <linux/gpio/driver.h>

#include <linux/interrupt.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

​

/* EIC registers definition */

#define SPRD_PMIC_EIC_DATA      0x0

#define SPRD_PMIC_EIC_DMSK      0x4

#define SPRD_PMIC_EIC_IEV       0x14

#define SPRD_PMIC_EIC_IE        0x18

#define SPRD_PMIC_EIC_RIS       0x1c

#define SPRD_PMIC_EIC_MIS       0x20

#define SPRD_PMIC_EIC_IC        0x24

#define SPRD_PMIC_EIC_TRIG      0x28

#define SPRD_PMIC_EIC_CTRL0     0x40

​

/*

 * The PMIC EIC controller only has one bank, and each bank now can contain

 * 16 EICs.

 */

#define SPRD_PMIC_EIC_PER_BANK_NR   16

#define SPRD_PMIC_EIC_NR        SPRD_PMIC_EIC_PER_BANK_NR

#define SPRD_PMIC_EIC_DATA_MASK     GENMASK(15, 0)

#define SPRD_PMIC_EIC_BIT(x)        ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))

#define SPRD_PMIC_EIC_DBNC_MASK     GENMASK(11, 0)

​

/*

 * These registers are modified under the irq bus lock and cached to avoid

 * unnecessary writes in bus_sync_unlock.

 */

enum {

    REG_IEV,

    REG_IE,

    REG_TRIG,

    CACHE_NR_REGS

};

​

/**

 * struct sprd_pmic_eic - PMIC EIC controller

 * @chip: the gpio_chip structure.

 * @intc: the irq_chip structure.

 * @regmap: the regmap from the parent device.

 * @offset: the EIC controller's offset address of the PMIC.

 * @reg: the array to cache the EIC registers.

 * @buslock: for bus lock/sync and unlock.

 * @irq: the interrupt number of the PMIC EIC conteroller.

 */

struct sprd_pmic_eic {

    struct gpio_chip chip;

    struct irq_chip intc;

    struct regmap *map;

    u32 offset;

    u8 reg[CACHE_NR_REGS];

    struct mutex buslock;