linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Intel Whiskey Cove PMIC GPIO Driver

 *

 * This driver is written based on gpio-crystalcove.c

 *

 * Copyright (C) 2016 Intel Corporation. All rights reserved.

 */

​

#include <linux/bitops.h>

#include <linux/gpio/driver.h>

#include <linux/interrupt.h>

#include <linux/mfd/intel_soc_pmic.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/seq_file.h>

​

/*

 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:

 * Bank 0: Pin  0 - 6

 * Bank 1: Pin  7 - 10

 * Bank 2: Pin 11 - 12

 * Each pin has one output control register and one input control register.

 */

#define BANK0_NR_PINS       7

#define BANK1_NR_PINS       4

#define BANK2_NR_PINS       2

#define WCOVE_GPIO_NUM      (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)

#define WCOVE_VGPIO_NUM     94

/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */

#define GPIO_OUT_CTRL_BASE  0x4e44

/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */

#define GPIO_IN_CTRL_BASE   0x4e51

​

/*

 * GPIO interrupts are organized in two groups:

 * Group 0: Bank 0 pins (Pin 0 - 6)

 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)

 * Each group has two registers (one bit per pin): status and mask.

 */

#define GROUP0_NR_IRQS      7

#define GROUP1_NR_IRQS      6

#define IRQ_MASK_BASE       0x4e19

#define IRQ_STATUS_BASE     0x4e0b

#define GPIO_IRQ0_MASK      GENMASK(6, 0)

#define GPIO_IRQ1_MASK      GENMASK(5, 0)

#define UPDATE_IRQ_TYPE     BIT(0)

#define UPDATE_IRQ_MASK     BIT(1)

​

#define CTLI_INTCNT_DIS     (0 << 1)

#define CTLI_INTCNT_NE      (1 << 1)

#define CTLI_INTCNT_PE      (2 << 1)

#define CTLI_INTCNT_BE      (3 << 1)

​

#define CTLO_DIR_IN     (0 << 5)

#define CTLO_DIR_OUT        (1 << 5)

​

#define CTLO_DRV_MASK       (1 << 4)

#define CTLO_DRV_OD     (0 << 4)

#define CTLO_DRV_CMOS       (1 << 4)

​

#define CTLO_DRV_REN        (1 << 3)