linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2003-2015 Broadcom Corporation

 * All Rights Reserved

 */

​

#include <linux/gpio/driver.h>

#include <linux/platform_device.h>

#include <linux/of_device.h>

#include <linux/module.h>

#include <linux/irq.h>

#include <linux/interrupt.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/acpi.h>

​

/*

 * XLP GPIO has multiple 32 bit registers for each feature where each register

 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96

 * require 3 32-bit registers for each feature.

 * Here we only define offset of the first register for each feature. Offset of

 * the registers for pins greater than 32 can be calculated as following(Use

 * GPIO_INT_STAT as example):

 *

 * offset = (gpio / XLP_GPIO_REGSZ) * 4;

 * reg_addr = addr + offset;

 *

 * where addr is base address of the that feature register and gpio is the pin.

 */

#define GPIO_OUTPUT_EN      0x00

#define GPIO_PADDRV     0x08

#define GPIO_INT_EN00       0x18

#define GPIO_INT_EN10       0x20

#define GPIO_INT_EN20       0x28

#define GPIO_INT_EN30       0x30

#define GPIO_INT_POL        0x38

#define GPIO_INT_TYPE       0x40

#define GPIO_INT_STAT       0x48

​

#define GPIO_9XX_BYTESWAP   0X00

#define GPIO_9XX_CTRL       0X04

#define GPIO_9XX_OUTPUT_EN  0x14

#define GPIO_9XX_PADDRV     0x24

/*

 * Only for 4 interrupt enable reg are defined for now,

 * total reg available are 12.

 */

#define GPIO_9XX_INT_EN00   0x44

#define GPIO_9XX_INT_EN10   0x54

#define GPIO_9XX_INT_EN20   0x64

#define GPIO_9XX_INT_EN30   0x74

#define GPIO_9XX_INT_POL    0x104

#define GPIO_9XX_INT_TYPE   0x114

#define GPIO_9XX_INT_STAT   0x124

​

#define GPIO_3XX_INT_EN00   0x18

#define GPIO_3XX_INT_EN10   0x20

#define GPIO_3XX_INT_EN20   0x28

#define GPIO_3XX_INT_EN30   0x30

#define GPIO_3XX_INT_POL    0x78

#define GPIO_3XX_INT_TYPE   0x80

#define GPIO_3XX_INT_STAT   0x88

​

/* Interrupt type register mask */