linux-imx

/*

 * Xilinx Zynq GPIO device driver

 *

 * Copyright (C) 2009 - 2014 Xilinx, Inc.

 *

 * This program is free software; you can redistribute it and/or modify it under

 * the terms of the GNU General Public License as published by the Free Software

 * Foundation; either version 2 of the License, or (at your option) any later

 * version.

 */

​

#include <linux/bitops.h>

#include <linux/clk.h>

#include <linux/gpio/driver.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/of.h>

​

#define DRIVER_NAME "zynq-gpio"

​

/* Maximum banks */

#define ZYNQ_GPIO_MAX_BANK  4

#define ZYNQMP_GPIO_MAX_BANK    6

​

#define ZYNQ_GPIO_BANK0_NGPIO   32

#define ZYNQ_GPIO_BANK1_NGPIO   22

#define ZYNQ_GPIO_BANK2_NGPIO   32

#define ZYNQ_GPIO_BANK3_NGPIO   32

​

#define ZYNQMP_GPIO_BANK0_NGPIO 26

#define ZYNQMP_GPIO_BANK1_NGPIO 26

#define ZYNQMP_GPIO_BANK2_NGPIO 26

#define ZYNQMP_GPIO_BANK3_NGPIO 32

#define ZYNQMP_GPIO_BANK4_NGPIO 32

#define ZYNQMP_GPIO_BANK5_NGPIO 32

​

#define ZYNQ_GPIO_NR_GPIOS  118

#define ZYNQMP_GPIO_NR_GPIOS    174

​

#define ZYNQ_GPIO_BANK0_PIN_MIN(str)    0

#define ZYNQ_GPIO_BANK0_PIN_MAX(str)    (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \

                    ZYNQ##str##_GPIO_BANK0_NGPIO - 1)

#define ZYNQ_GPIO_BANK1_PIN_MIN(str)    (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)

#define ZYNQ_GPIO_BANK1_PIN_MAX(str)    (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \

                    ZYNQ##str##_GPIO_BANK1_NGPIO - 1)

#define ZYNQ_GPIO_BANK2_PIN_MIN(str)    (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)

#define ZYNQ_GPIO_BANK2_PIN_MAX(str)    (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \

                    ZYNQ##str##_GPIO_BANK2_NGPIO - 1)

#define ZYNQ_GPIO_BANK3_PIN_MIN(str)    (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)

#define ZYNQ_GPIO_BANK3_PIN_MAX(str)    (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \

                    ZYNQ##str##_GPIO_BANK3_NGPIO - 1)

#define ZYNQ_GPIO_BANK4_PIN_MIN(str)    (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)

#define ZYNQ_GPIO_BANK4_PIN_MAX(str)    (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \

                    ZYNQ##str##_GPIO_BANK4_NGPIO - 1)

#define ZYNQ_GPIO_BANK5_PIN_MIN(str)    (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)

#define ZYNQ_GPIO_BANK5_PIN_MAX(str)    (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \

                    ZYNQ##str##_GPIO_BANK5_NGPIO - 1)

​

/* Register offsets for the GPIO device */

/* LSW Mask & Data -WO */

#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))

/* MSW Mask & Data -WO */

#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))

/* Data Register-RW */

#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))

#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))

/* Direction mode reg-RW */

#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))

/* Output enable reg-RW */

#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))

/* Interrupt mask reg-RO */

#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))

/* Interrupt enable reg-WO */

#define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))

/* Interrupt disable reg-WO */

#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))

/* Interrupt status reg-RO */

#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))

/* Interrupt type reg-RW */

#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))

/* Interrupt polarity reg-RW */

#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))

/* Interrupt on any, reg-RW */

#define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))

​

/* Disable all interrupts mask */

#define ZYNQ_GPIO_IXR_DISABLE_ALL   0xFFFFFFFF

​