linux-imx

// SPDX-License-Identifier: GPL-2.0

/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */

/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */

/* Copyright 2019 Collabora ltd. */

#include <linux/bitfield.h>

#include <linux/bitmap.h>

#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/platform_device.h>

​

#include "panfrost_device.h"

#include "panfrost_features.h"

#include "panfrost_issues.h"

#include "panfrost_gpu.h"

#include "panfrost_regs.h"

​

#define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)

#define gpu_read(dev, reg) readl(dev->iomem + reg)

​

static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)

{

    struct panfrost_device *pfdev = data;

    u32 state = gpu_read(pfdev, GPU_INT_STAT);

    u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);

​

    if (!state)

        return IRQ_NONE;

​

    if (state & GPU_IRQ_MASK_ERROR) {

        u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;

        address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);

​

        dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",

             fault_status & 0xFF, panfrost_exception_name(pfdev, fault_status),

             address);

​

        if (state & GPU_IRQ_MULTIPLE_FAULT)

            dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");

​

        gpu_write(pfdev, GPU_INT_MASK, 0);

    }

​

    gpu_write(pfdev, GPU_INT_CLEAR, state);

​

    return IRQ_HANDLED;

}

​

int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)

{

    int ret;

    u32 val;

​

    gpu_write(pfdev, GPU_INT_MASK, 0);

    gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);

    gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);

​

    ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,

        val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);

​

    if (ret) {

        dev_err(pfdev->dev, "gpu soft reset timed out\n");

        return ret;

    }

​

    gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);

    gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL);

​

    return 0;

}

​

static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)

{

    u32 quirks = 0;

​

    if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||

        panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))

        quirks |= SC_LS_PAUSEBUFFER_DISABLE;

​

    if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))

        quirks |= SC_SDC_DISABLE_OQ_DISCARD;

​

    if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))

        quirks |= SC_ENABLE_TEXGRD_FLAGS;

​

    if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {

        if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */

            quirks |= SC_LS_ATTR_CHECK_DISABLE;

        else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */

            quirks |= SC_LS_ALLOW_ATTR_TYPES;