Source of tilcdc_regs.h - linux-imx - PHYTEC BitBucket (Stash)

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/* * Copyright (C) 2012 Texas Instruments * Author: Rob Clark <robdclark@gmail.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program.  If not, see <http://www.gnu.org/licenses/>. */​#ifndef __TILCDC_REGS_H__#define __TILCDC_REGS_H__​/* LCDC register definitions, based on da8xx-fb */​#include <linux/bitops.h>​#include "tilcdc_drv.h"​/* LCDC Status Register */#define LCDC_END_OF_FRAME1                       BIT(9)#define LCDC_END_OF_FRAME0                       BIT(8)#define LCDC_PL_LOAD_DONE                        BIT(6)#define LCDC_FIFO_UNDERFLOW                      BIT(5)#define LCDC_SYNC_LOST                           BIT(2)#define LCDC_FRAME_DONE                          BIT(0)​/* LCDC DMA Control Register */#define LCDC_DMA_BURST_SIZE(x)                   ((x) << 4)#define LCDC_DMA_BURST_SIZE_MASK                 ((0x7) << 4)#define LCDC_DMA_BURST_1                         0x0#define LCDC_DMA_BURST_2                         0x1#define LCDC_DMA_BURST_4                         0x2#define LCDC_DMA_BURST_8                         0x3#define LCDC_DMA_BURST_16                        0x4#define LCDC_DMA_FIFO_THRESHOLD(x)               ((x) << 8)#define LCDC_DMA_FIFO_THRESHOLD_MASK             ((0x3) << 8)#define LCDC_V1_END_OF_FRAME_INT_ENA             BIT(2)#define LCDC_V2_END_OF_FRAME0_INT_ENA            BIT(8)#define LCDC_V2_END_OF_FRAME1_INT_ENA            BIT(9)#define LCDC_DUAL_FRAME_BUFFER_ENABLE            BIT(0)​/* LCDC Control Register */#define LCDC_CLK_DIVISOR(x)                      ((x) << 8)#define LCDC_CLK_DIVISOR_MASK                    ((0xFF) << 8)#define LCDC_RASTER_MODE                         0x01​/* LCDC Raster Control Register */#define LCDC_PALETTE_LOAD_MODE(x)                ((x) << 20)#define LCDC_PALETTE_LOAD_MODE_MASK              ((0x3) << 20)#define PALETTE_AND_DATA                         0x00#define PALETTE_ONLY                             0x01#define DATA_ONLY                                0x02​#define LCDC_MONO_8BIT_MODE                      BIT(9)#define LCDC_RASTER_ORDER                        BIT(8)#define LCDC_TFT_MODE                            BIT(7)#define LCDC_V1_UNDERFLOW_INT_ENA                BIT(6)#define LCDC_V2_UNDERFLOW_INT_ENA                BIT(5)#define LCDC_V1_PL_INT_ENA                       BIT(4)#define LCDC_V2_PL_INT_ENA                       BIT(6)#define LCDC_V1_SYNC_LOST_INT_ENA                BIT(5)#define LCDC_V1_FRAME_DONE_INT_ENA               BIT(3)#define LCDC_MONOCHROME_MODE                     BIT(1)#define LCDC_RASTER_ENABLE                       BIT(0)#define LCDC_TFT_ALT_ENABLE                      BIT(23)#define LCDC_STN_565_ENABLE                      BIT(24)#define LCDC_V2_DMA_CLK_EN                       BIT(2)#define LCDC_V2_LIDD_CLK_EN                      BIT(1)#define LCDC_V2_CORE_CLK_EN                      BIT(0)#define LCDC_V2_LPP_B10                          26#define LCDC_V2_TFT_24BPP_MODE                   BIT(25)#define LCDC_V2_TFT_24BPP_UNPACK                 BIT(26)​/* LCDC Raster Timing 2 Register */#define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)#define LCDC_AC_BIAS_TRANSITIONS_PER_INT_MASK    ((0xF) << 16)#define LCDC_AC_BIAS_FREQUENCY(x)                ((x) << 8)#define LCDC_AC_BIAS_FREQUENCY_MASK              ((0xFF) << 8)#define LCDC_SYNC_CTRL                           BIT(25)#define LCDC_SYNC_EDGE                           BIT(24)#define LCDC_INVERT_PIXEL_CLOCK                  BIT(22)#define LCDC_INVERT_HSYNC                        BIT(21)#define LCDC_INVERT_VSYNC                        BIT(20)#define LCDC_LPP_B10                             BIT(26)