linux-imx

/*

 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04

 * IDE driver for Linux.

 *

 * Copyright (c) 2000-2002 Vojtech Pavlik

 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz

 *

 * Based on the work of:

 *      Andre Hedrick

 */

​

/*

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 */

​

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/init.h>

#include <linux/ide.h>

​

#define DRV_NAME "amd74xx"

​

enum {

    AMD_IDE_CONFIG      = 0x41,

    AMD_CABLE_DETECT    = 0x42,

    AMD_DRIVE_TIMING    = 0x48,

    AMD_8BIT_TIMING     = 0x4e,

    AMD_ADDRESS_SETUP   = 0x4c,

    AMD_UDMA_TIMING     = 0x50,

};

​

static unsigned int amd_80w;

static unsigned int amd_clock;

​

static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };

​

static inline u8 amd_offset(struct pci_dev *dev)

{

    return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;

}

​

/*

 * amd_set_speed() writes timing values to the chipset registers

 */

​

static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,

              struct ide_timing *timing)

{

    u8 t = 0, offset = amd_offset(dev);

​

    pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);

    t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));

    pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);

​

    pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),

        ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));

​

    pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),

        ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));

​

    switch (udma_mask) {

    case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;

    case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;

    case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;

    case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;

    default: return;

    }

​

    if (timing->udma)

        pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t);

}

​

/*

 * amd_set_drive() computes timing values and configures the chipset

 * to a desired transfer mode.  It also can be called by upper layers.

 */

​

static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)

{

    struct pci_dev *dev = to_pci_dev(hwif->dev);

    ide_drive_t *peer = ide_get_pair_dev(drive);

    struct ide_timing t, p;

    int T, UT;

    u8 udma_mask = hwif->ultra_mask;

    const u8 speed = drive->dma_mode;

​

    T = 1000000000 / amd_clock;

    UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);