linux-imx

/*

 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.

 *           Due to massive hardware bugs, UltraDMA is only supported

 *           on the 646U2 and not on the 646U.

 *

 * Copyright (C) 1998       Eddie C. Dost  (ecd@skynet.be)

 * Copyright (C) 1998       David S. Miller (davem@redhat.com)

 *

 * Copyright (C) 1999-2002  Andre Hedrick <andre@linux-ide.org>

 * Copyright (C) 2007-2010  Bartlomiej Zolnierkiewicz

 * Copyright (C) 2007,2009  MontaVista Software, Inc. <source@mvista.com>

 */

​

#include <linux/module.h>

#include <linux/types.h>

#include <linux/pci.h>

#include <linux/ide.h>

#include <linux/init.h>

​

#include <asm/io.h>

​

#define DRV_NAME "cmd64x"

​

/*

 * CMD64x specific registers definition.

 */

#define CFR     0x50

#define   CFR_INTR_CH0      0x04

​

#define CMDTIM      0x52

#define ARTTIM0     0x53

#define DRWTIM0     0x54

#define ARTTIM1     0x55

#define DRWTIM1     0x56

#define ARTTIM23    0x57

#define   ARTTIM23_DIS_RA2  0x04

#define   ARTTIM23_DIS_RA3  0x08

#define   ARTTIM23_INTR_CH1 0x10

#define DRWTIM2     0x58

#define BRST        0x59

#define DRWTIM3     0x5b

​

#define BMIDECR0    0x70

#define MRDMODE     0x71

#define   MRDMODE_INTR_CH0  0x04

#define   MRDMODE_INTR_CH1  0x08

#define UDIDETCR0   0x73

#define DTPR0       0x74

#define BMIDECR1    0x78

#define BMIDECSR    0x79

#define UDIDETCR1   0x7B

#define DTPR1       0x7C

​

static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)

{

    ide_hwif_t *hwif = drive->hwif;

    struct pci_dev *dev = to_pci_dev(drive->hwif->dev);

    int bus_speed = ide_pci_clk ? ide_pci_clk : 33;

    const unsigned long T = 1000000 / bus_speed;

    static const u8 recovery_values[] =

        {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};

    static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};

    static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};

    static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};

    struct ide_timing t;

    u8 arttim = 0;

​

    ide_timing_compute(drive, mode, &t, T, 0);

​

    /*

     * In case we've got too long recovery phase, try to lengthen

     * the active phase

     */

    if (t.recover > 16) {

        t.active += t.recover - 16;

        t.recover = 16;

    }

    if (t.active > 16)      /* shouldn't actually happen... */

        t.active = 16;

​

    /*

     * Convert values to internal chipset representation

     */

    t.recover = recovery_values[t.recover];

    t.active &= 0x0f;

​

    /* Program the active/recovery counts into the DRWTIM register */

    pci_write_config_byte(dev, drwtim_regs[drive->dn],

                  (t.active << 4) | t.recover);

​

    /*

     * The primary channel has individual address setup timing registers